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/*
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* FreeRTOS Kernel Port For Nuclei RISC-V Processor
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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#include "riscv_encoding.h"
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#include "cpufeature.h"
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#ifndef __riscv_32e
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#define portRegNum 32
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#else
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#define portRegNum 14
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#endif
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#define portCONTEXT_SIZE ( portRegNum * REGBYTES )
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.section .text.entry
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.align 8
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// If you want to use SMP freertos
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// configNUMBER_OF_CORES must be defined to the number of cores in your system.
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// If you define configNUMBER_OF_CORES using -D option, you must make sure that
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// asm option must contains this macro defined
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#ifndef configNUMBER_OF_CORES
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#define configNUMBER_OF_CORES 1
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#endif
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.extern xPortTaskSwitch
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#if ( configNUMBER_OF_CORES == 1 )
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.extern pxCurrentTCB
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#else
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.extern pxCurrentTCBs
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#endif
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.global prvPortStartFirstTask
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/**
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* \brief Global interrupt disabled
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* \details
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* This function disable global interrupt.
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* \remarks
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* - All the interrupt requests will be ignored by CPU.
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*/
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.macro DISABLE_MIE
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csrc CSR_MSTATUS, MSTATUS_MIE
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.endm
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/**
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* \brief Macro for context save
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* \details
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* This macro save ABI defined caller saved registers in the stack.
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* \remarks
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* - This Macro could use to save context when you enter to interrupt
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* or exception
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*/
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/* Save caller registers */
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.macro SAVE_CONTEXT
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#if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
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#else
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csrrw sp, CSR_MSCRATCHCSWL, sp
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/* Allocate stack space for context saving */
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#ifndef __riscv_32e
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addi sp, sp, -20*REGBYTES
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#else
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addi sp, sp, -14*REGBYTES
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#endif /* __riscv_32e */
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STORE x1, 0*REGBYTES(sp)
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STORE x4, 1*REGBYTES(sp)
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STORE x5, 2*REGBYTES(sp)
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STORE x6, 3*REGBYTES(sp)
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STORE x7, 4*REGBYTES(sp)
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STORE x10, 5*REGBYTES(sp)
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STORE x11, 6*REGBYTES(sp)
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STORE x12, 7*REGBYTES(sp)
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STORE x13, 8*REGBYTES(sp)
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STORE x14, 9*REGBYTES(sp)
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STORE x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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STORE x16, 14*REGBYTES(sp)
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STORE x17, 15*REGBYTES(sp)
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STORE x28, 16*REGBYTES(sp)
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STORE x29, 17*REGBYTES(sp)
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STORE x30, 18*REGBYTES(sp)
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STORE x31, 19*REGBYTES(sp)
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#endif /* __riscv_32e */
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#endif
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.endm
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/**
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* \brief Macro for restore caller registers
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* \details
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* This macro restore ABI defined caller saved registers from stack.
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* \remarks
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* - You could use this macro to restore context before you want return
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* from interrupt or exeception
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*/
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/* Restore caller registers */
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.macro RESTORE_CONTEXT
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#if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
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#else
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LOAD x1, 0*REGBYTES(sp)
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LOAD x4, 1*REGBYTES(sp)
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LOAD x5, 2*REGBYTES(sp)
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LOAD x6, 3*REGBYTES(sp)
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LOAD x7, 4*REGBYTES(sp)
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LOAD x10, 5*REGBYTES(sp)
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LOAD x11, 6*REGBYTES(sp)
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LOAD x12, 7*REGBYTES(sp)
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LOAD x13, 8*REGBYTES(sp)
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LOAD x14, 9*REGBYTES(sp)
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LOAD x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 14*REGBYTES(sp)
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LOAD x17, 15*REGBYTES(sp)
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LOAD x28, 16*REGBYTES(sp)
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LOAD x29, 17*REGBYTES(sp)
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LOAD x30, 18*REGBYTES(sp)
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LOAD x31, 19*REGBYTES(sp)
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/* De-allocate the stack space */
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addi sp, sp, 20*REGBYTES
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#else
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/* De-allocate the stack space */
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addi sp, sp, 14*REGBYTES
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#endif /* __riscv_32e */
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csrrw sp, CSR_MSCRATCHCSWL, sp
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#endif
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.endm
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/**
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* \brief Macro for save necessary CSRs to stack
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* \details
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* This macro store MCAUSE, MEPC, MSUBM to stack.
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*/
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.macro SAVE_CSR_CONTEXT
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#if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
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#else
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/* Store CSR mcause to stack using pushmcause */
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csrrwi x0, CSR_PUSHMCAUSE, 11
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/* Store CSR mepc to stack using pushmepc */
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csrrwi x0, CSR_PUSHMEPC, 12
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/* Store CSR msub to stack using pushmsub */
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csrrwi x0, CSR_PUSHMSUBM, 13
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#endif
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.endm
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/**
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* \brief Macro for restore necessary CSRs from stack
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* \details
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* This macro restore MSUBM, MEPC, MCAUSE from stack.
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*/
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.macro RESTORE_CSR_CONTEXT
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#if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
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#else
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LOAD x5, 13*REGBYTES(sp)
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csrw CSR_MSUBM, x5
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LOAD x5, 12*REGBYTES(sp)
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csrw CSR_MEPC, x5
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LOAD x5, 11*REGBYTES(sp)
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csrw CSR_MCAUSE, x5
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#endif
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.endm
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/**
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* \brief Exception/NMI Entry
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* \details
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* This function provide common entry functions for exception/nmi.
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* \remarks
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* This function provide a default exception/nmi entry.
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* ABI defined caller save register and some CSR registers
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* to be saved before enter interrupt handler and be restored before return.
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*/
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.section .text.trap
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/* In CLIC mode, the exeception entry must be 64bytes aligned */
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.align 6
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.global exc_entry
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.type exc_entry, @function
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exc_entry:
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/* Save the caller saving registers (context) */
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SAVE_CONTEXT
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/* Save the necessary CSR registers */
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SAVE_CSR_CONTEXT
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/*
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* Set the exception handler function arguments
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* argument 1: mcause value
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* argument 2: current stack point(SP) value
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*/
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csrr a0, mcause
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mv a1, sp
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/*
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* TODO: Call the exception handler function
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* By default, the function template is provided in
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* system_Device.c, you can adjust it as you want
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*/
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call core_exception_handler
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/* Restore the necessary CSR registers */
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RESTORE_CSR_CONTEXT
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/* Restore the caller saving registers (context) */
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RESTORE_CONTEXT
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/* Return to regular code */
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#if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
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csrrwi x0, CSR_POPXRET, 0
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#else
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mret
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#endif
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.size exc_entry, . - exc_entry
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/**
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* \brief Non-Vector Interrupt Entry
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* \details
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* This function provide common entry functions for handling
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* non-vector interrupts
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* \remarks
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* This function provide a default non-vector interrupt entry.
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* ABI defined caller save register and some CSR registers need
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* to be saved before enter interrupt handler and be restored before return.
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*/
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.section .text.irq
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/* In CLIC mode, the interrupt entry must be 4bytes aligned */
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.align 2
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.global irq_entry
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.type irq_entry, @function
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/* This label will be set to MTVT2 register */
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irq_entry:
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/* Save the caller saving registers (context) */
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SAVE_CONTEXT
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/* Save the necessary CSR registers */
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SAVE_CSR_CONTEXT
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/* This special CSR read/write operation, which is actually
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* claim the CLIC to find its pending highest ID, if the ID
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* is not 0, then automatically enable the mstatus.MIE, and
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* jump to its vector-entry-label, and update the link register
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*/
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csrrw ra, CSR_JALMNXTI, ra
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/* Critical section with interrupts disabled */
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DISABLE_MIE
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/* Restore the necessary CSR registers */
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RESTORE_CSR_CONTEXT
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/* Restore the caller saving registers (context) */
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RESTORE_CONTEXT
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/* Return to regular code */
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#if defined(ECLIC_HW_CTX_AUTO) && defined(CFG_HAS_ECLICV2)
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csrrwi x0, CSR_POPXRET, 0
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#else
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mret
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#endif
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.size irq_entry, . - irq_entry
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/* Default Handler for Exceptions / Interrupts */
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.global default_intexc_handler
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.type default_intexc_handler, @function
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Undef_Handler:
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default_intexc_handler:
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1:
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j 1b
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.size default_intexc_handler, . - default_intexc_handler
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the stack
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for lazy saving of FPU registers. */
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.type prvPortStartFirstTask, @function
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.align 3
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prvPortStartFirstTask:
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/* Setup Interrupt Stack using
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The stack that was used by main()
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before the scheduler is started is
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no longer required after the scheduler is started.
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Interrupt stack pointer is stored in CSR_MSCRATCH */
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#if defined(SMP_CPU_CNT) && (SMP_CPU_CNT > 1)
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/* get correct sp for each cpu
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* each stack size is __STACK_SIZE
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* defined in linker script */
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lui t1, %hi(__STACK_SIZE)
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addi t1, t1, %lo(__STACK_SIZE)
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la t0, _sp
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csrr a0, CSR_MHARTID
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andi a0, a0, 0xFF
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li a1, 0
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1:
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beq a0, a1, 2f
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sub t0, t0, t1
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addi a1, a1, 1
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j 1b
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2:
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#else
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la t0, _sp // TODO need to consider SMP case
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#endif
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csrw CSR_MSCRATCH, t0
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#if ( configNUMBER_OF_CORES == 1 )
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LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */
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#else
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la t0, pxCurrentTCBs /* Load pxCurrentTCBs[core] */
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csrr t1, CSR_MHARTID
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slli t1, t1, LOG_REGBYTES
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add t0, t0, t1
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LOAD t0, 0(t0)
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#endif
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LOAD sp, 0x0(t0) /* Read sp from first TCB member */
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/* Pop PC from stack and set MEPC */
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LOAD t0, 0 * REGBYTES(sp)
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csrw CSR_MEPC, t0
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/* Pop mstatus from stack and set it */
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LOAD t0, (portRegNum - 1) * REGBYTES(sp)
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csrw CSR_MSTATUS, t0
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/* Interrupt still disable here */
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/* Restore Registers from Stack */
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LOAD x1, 1 * REGBYTES(sp) /* RA */
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LOAD x5, 2 * REGBYTES(sp)
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LOAD x6, 3 * REGBYTES(sp)
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LOAD x7, 4 * REGBYTES(sp)
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LOAD x8, 5 * REGBYTES(sp)
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LOAD x9, 6 * REGBYTES(sp)
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LOAD x10, 7 * REGBYTES(sp)
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LOAD x11, 8 * REGBYTES(sp)
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LOAD x12, 9 * REGBYTES(sp)
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LOAD x13, 10 * REGBYTES(sp)
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LOAD x14, 11 * REGBYTES(sp)
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LOAD x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 13 * REGBYTES(sp)
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LOAD x17, 14 * REGBYTES(sp)
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LOAD x18, 15 * REGBYTES(sp)
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LOAD x19, 16 * REGBYTES(sp)
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LOAD x20, 17 * REGBYTES(sp)
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LOAD x21, 18 * REGBYTES(sp)
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LOAD x22, 19 * REGBYTES(sp)
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LOAD x23, 20 * REGBYTES(sp)
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LOAD x24, 21 * REGBYTES(sp)
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LOAD x25, 22 * REGBYTES(sp)
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LOAD x26, 23 * REGBYTES(sp)
|
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LOAD x27, 24 * REGBYTES(sp)
|
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LOAD x28, 25 * REGBYTES(sp)
|
||||
LOAD x29, 26 * REGBYTES(sp)
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LOAD x30, 27 * REGBYTES(sp)
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LOAD x31, 28 * REGBYTES(sp)
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||||
#endif
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||||
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addi sp, sp, portCONTEXT_SIZE
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||||
mret
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||||
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||||
.size prvPortStartFirstTask, . - prvPortStartFirstTask
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||||
|
||||
.align 2
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||||
.global eclic_msip_handler
|
||||
.type eclic_msip_handler, @function
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||||
eclic_msip_handler:
|
||||
#if defined(__riscv_flen)
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addi sp, sp, -(2 * REGBYTES)
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||||
STORE t0, 0 * REGBYTES(sp)
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||||
STORE t1, 1 * REGBYTES(sp)
|
||||
_save_fp_stack:
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||||
csrr t0, CSR_MSTATUS
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||||
li t1, MSTATUS_FS_DIRTY
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||||
and t0,t0,t1
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||||
#if defined(__riscv_vector)
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||||
bne t0, t1, _save_vector_stack
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||||
#else
|
||||
bne t0, t1, _save_integer_stack
|
||||
#endif
|
||||
LOAD t0, 0 * REGBYTES(sp)
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||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
addi sp, sp, (2 * REGBYTES)
|
||||
|
||||
/* Save fp registers and fcsr and 3 reserved reg space, make sure 16 bytes aligned */
|
||||
addi sp, sp, -(5 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
csrr t0, CSR_FCSR
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||||
STORE t0, 1 * REGBYTES(sp)
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
addi sp, sp, (1 * REGBYTES)
|
||||
addi sp, sp, -(32 * FPREGBYTES)
|
||||
FPSTORE f0 , 0 * FPREGBYTES(sp)
|
||||
FPSTORE f1 , 1 * FPREGBYTES(sp)
|
||||
FPSTORE f2 , 2 * FPREGBYTES(sp)
|
||||
FPSTORE f3 , 3 * FPREGBYTES(sp)
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||||
FPSTORE f4 , 4 * FPREGBYTES(sp)
|
||||
FPSTORE f5 , 5 * FPREGBYTES(sp)
|
||||
FPSTORE f6 , 6 * FPREGBYTES(sp)
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||||
FPSTORE f7 , 7 * FPREGBYTES(sp)
|
||||
FPSTORE f8 , 8 * FPREGBYTES(sp)
|
||||
FPSTORE f9 , 9 * FPREGBYTES(sp)
|
||||
FPSTORE f10, 10 * FPREGBYTES(sp)
|
||||
FPSTORE f11, 11 * FPREGBYTES(sp)
|
||||
FPSTORE f12, 12 * FPREGBYTES(sp)
|
||||
FPSTORE f13, 13 * FPREGBYTES(sp)
|
||||
FPSTORE f14, 14 * FPREGBYTES(sp)
|
||||
FPSTORE f15, 15 * FPREGBYTES(sp)
|
||||
FPSTORE f16, 16 * FPREGBYTES(sp)
|
||||
FPSTORE f17, 17 * FPREGBYTES(sp)
|
||||
FPSTORE f18, 18 * FPREGBYTES(sp)
|
||||
FPSTORE f19, 19 * FPREGBYTES(sp)
|
||||
FPSTORE f20, 20 * FPREGBYTES(sp)
|
||||
FPSTORE f21, 21 * FPREGBYTES(sp)
|
||||
FPSTORE f22, 22 * FPREGBYTES(sp)
|
||||
FPSTORE f23, 23 * FPREGBYTES(sp)
|
||||
FPSTORE f24, 24 * FPREGBYTES(sp)
|
||||
FPSTORE f25, 25 * FPREGBYTES(sp)
|
||||
FPSTORE f26, 26 * FPREGBYTES(sp)
|
||||
FPSTORE f27, 27 * FPREGBYTES(sp)
|
||||
FPSTORE f28, 28 * FPREGBYTES(sp)
|
||||
FPSTORE f29, 29 * FPREGBYTES(sp)
|
||||
FPSTORE f30, 30 * FPREGBYTES(sp)
|
||||
FPSTORE f31, 31 * FPREGBYTES(sp)
|
||||
#endif
|
||||
#if defined(__riscv_vector)
|
||||
addi sp, sp, -(2 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
STORE t1, 1 * REGBYTES(sp)
|
||||
_save_vector_stack:
|
||||
csrr t0, CSR_MSTATUS
|
||||
li t1, MSTATUS_VS_DIRTY
|
||||
and t0,t0,t1
|
||||
bne t0, t1, _save_integer_stack
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
addi sp, sp, (2 * REGBYTES)
|
||||
|
||||
/* Save vector registers and vtype/vl/vstart/vcsr */
|
||||
addi sp, sp, -(6 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
STORE t1, 1 * REGBYTES(sp)
|
||||
csrr t0, CSR_VSTART
|
||||
STORE t0, 2 * REGBYTES(sp)
|
||||
csrr t0, CSR_VTYPE
|
||||
STORE t0, 3 * REGBYTES(sp)
|
||||
csrr t0, CSR_VL
|
||||
STORE t0, 4 * REGBYTES(sp)
|
||||
csrr t0, CSR_VCSR
|
||||
STORE t0, 5 * REGBYTES(sp)
|
||||
|
||||
mv t1, sp
|
||||
csrr t0, CSR_VLENB
|
||||
slli t0, t0, 5
|
||||
/* t1 is the new temp stack where t0, t1 saved */
|
||||
sub t1, t1, t0
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
STORE t0, 0 * REGBYTES(t1)
|
||||
LOAD t0, 1 * REGBYTES(sp)
|
||||
STORE t0, 1 * REGBYTES(t1)
|
||||
mv sp, t1
|
||||
/* new sp -> t1 to save vector registers */
|
||||
addi t1, t1, (2 * REGBYTES)
|
||||
vsetvli t0, x0, e8, m8, ta, ma
|
||||
vse8.v v0, (t1)
|
||||
add t1, t1, t0
|
||||
vse8.v v8, (t1)
|
||||
add t1, t1, t0
|
||||
vse8.v v16, (t1)
|
||||
add t1, t1, t0
|
||||
vse8.v v24, (t1)
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
addi sp, sp, (2 * REGBYTES)
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_flen) || defined(__riscv_vector)
|
||||
addi sp, sp, -(2 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
STORE t1, 1 * REGBYTES(sp)
|
||||
_save_integer_stack:
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
addi sp, sp, (2 * REGBYTES)
|
||||
#endif
|
||||
addi sp, sp, -portCONTEXT_SIZE
|
||||
STORE x1, 1 * REGBYTES(sp) /* RA */
|
||||
STORE x5, 2 * REGBYTES(sp)
|
||||
STORE x6, 3 * REGBYTES(sp)
|
||||
STORE x7, 4 * REGBYTES(sp)
|
||||
STORE x8, 5 * REGBYTES(sp)
|
||||
STORE x9, 6 * REGBYTES(sp)
|
||||
STORE x10, 7 * REGBYTES(sp)
|
||||
STORE x11, 8 * REGBYTES(sp)
|
||||
STORE x12, 9 * REGBYTES(sp)
|
||||
STORE x13, 10 * REGBYTES(sp)
|
||||
STORE x14, 11 * REGBYTES(sp)
|
||||
STORE x15, 12 * REGBYTES(sp)
|
||||
#ifndef __riscv_32e
|
||||
STORE x16, 13 * REGBYTES(sp)
|
||||
STORE x17, 14 * REGBYTES(sp)
|
||||
STORE x18, 15 * REGBYTES(sp)
|
||||
STORE x19, 16 * REGBYTES(sp)
|
||||
STORE x20, 17 * REGBYTES(sp)
|
||||
STORE x21, 18 * REGBYTES(sp)
|
||||
STORE x22, 19 * REGBYTES(sp)
|
||||
STORE x23, 20 * REGBYTES(sp)
|
||||
STORE x24, 21 * REGBYTES(sp)
|
||||
STORE x25, 22 * REGBYTES(sp)
|
||||
STORE x26, 23 * REGBYTES(sp)
|
||||
STORE x27, 24 * REGBYTES(sp)
|
||||
STORE x28, 25 * REGBYTES(sp)
|
||||
STORE x29, 26 * REGBYTES(sp)
|
||||
STORE x30, 27 * REGBYTES(sp)
|
||||
STORE x31, 28 * REGBYTES(sp)
|
||||
#endif
|
||||
/* Push mstatus to stack */
|
||||
csrr t0, CSR_MSTATUS
|
||||
STORE t0, (portRegNum - 1) * REGBYTES(sp)
|
||||
|
||||
/* Push additional registers */
|
||||
|
||||
/* Store sp to task stack */
|
||||
#if ( configNUMBER_OF_CORES == 1 )
|
||||
LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||
#else
|
||||
la t0, pxCurrentTCBs /* Load pxCurrentTCBs[core] */
|
||||
csrr t1, CSR_MHARTID
|
||||
slli t1, t1, LOG_REGBYTES
|
||||
add t0, t0, t1
|
||||
LOAD t0, 0(t0)
|
||||
#endif
|
||||
STORE sp, 0(t0)
|
||||
|
||||
csrr t0, CSR_MEPC
|
||||
STORE t0, 0(sp)
|
||||
jal xPortTaskSwitch
|
||||
|
||||
/* Switch task context */
|
||||
#if ( configNUMBER_OF_CORES == 1 )
|
||||
LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||
#else
|
||||
la t0, pxCurrentTCBs /* Load pxCurrentTCBs[core] */
|
||||
csrr t1, CSR_MHARTID
|
||||
slli t1, t1, LOG_REGBYTES
|
||||
add t0, t0, t1
|
||||
LOAD t0, 0(t0)
|
||||
#endif
|
||||
LOAD sp, 0x0(t0) /* Read sp from first TCB member */
|
||||
|
||||
/* Pop PC from stack and set MEPC */
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
csrw CSR_MEPC, t0
|
||||
/* Pop additional registers */
|
||||
|
||||
/* Pop mstatus from stack and set it */
|
||||
LOAD t0, (portRegNum - 1) * REGBYTES(sp)
|
||||
csrw CSR_MSTATUS, t0
|
||||
/* Interrupt still disable here */
|
||||
/* Restore Registers from Stack */
|
||||
LOAD x1, 1 * REGBYTES(sp) /* RA */
|
||||
LOAD x5, 2 * REGBYTES(sp)
|
||||
LOAD x6, 3 * REGBYTES(sp)
|
||||
LOAD x7, 4 * REGBYTES(sp)
|
||||
LOAD x8, 5 * REGBYTES(sp)
|
||||
LOAD x9, 6 * REGBYTES(sp)
|
||||
LOAD x10, 7 * REGBYTES(sp)
|
||||
LOAD x11, 8 * REGBYTES(sp)
|
||||
LOAD x12, 9 * REGBYTES(sp)
|
||||
LOAD x13, 10 * REGBYTES(sp)
|
||||
LOAD x14, 11 * REGBYTES(sp)
|
||||
LOAD x15, 12 * REGBYTES(sp)
|
||||
#ifndef __riscv_32e
|
||||
LOAD x16, 13 * REGBYTES(sp)
|
||||
LOAD x17, 14 * REGBYTES(sp)
|
||||
LOAD x18, 15 * REGBYTES(sp)
|
||||
LOAD x19, 16 * REGBYTES(sp)
|
||||
LOAD x20, 17 * REGBYTES(sp)
|
||||
LOAD x21, 18 * REGBYTES(sp)
|
||||
LOAD x22, 19 * REGBYTES(sp)
|
||||
LOAD x23, 20 * REGBYTES(sp)
|
||||
LOAD x24, 21 * REGBYTES(sp)
|
||||
LOAD x25, 22 * REGBYTES(sp)
|
||||
LOAD x26, 23 * REGBYTES(sp)
|
||||
LOAD x27, 24 * REGBYTES(sp)
|
||||
LOAD x28, 25 * REGBYTES(sp)
|
||||
LOAD x29, 26 * REGBYTES(sp)
|
||||
LOAD x30, 27 * REGBYTES(sp)
|
||||
LOAD x31, 28 * REGBYTES(sp)
|
||||
#endif
|
||||
|
||||
addi sp, sp, portCONTEXT_SIZE
|
||||
|
||||
#if defined(__riscv_vector)
|
||||
/* Pop vector stack if needed */
|
||||
addi sp, sp, -(2 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
STORE t1, 1 * REGBYTES(sp)
|
||||
_restore_vector_stack:
|
||||
csrr t0, CSR_MSTATUS
|
||||
li t1, MSTATUS_VS_DIRTY
|
||||
and t0,t0,t1
|
||||
#if defined(__riscv_flen)
|
||||
bne t0, t1, _restore_fp_stack
|
||||
#else
|
||||
bne t0, t1, _restore_done
|
||||
#endif
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
addi sp, sp, (2 * REGBYTES)
|
||||
|
||||
/* pop vector registers and vtype/vl/vstart/vcsr */
|
||||
addi sp, sp, -(3 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
STORE t1, 1 * REGBYTES(sp)
|
||||
STORE t2, 2 * REGBYTES(sp)
|
||||
mv t2, sp
|
||||
/* temp regs are stored in t2 stack top */
|
||||
addi sp, sp, (3 * REGBYTES)
|
||||
vsetvli t0, x0, e8, m8, ta, ma
|
||||
vle8.v v0, (sp)
|
||||
add sp, sp, t0
|
||||
vle8.v v8, (sp)
|
||||
add sp, sp, t0
|
||||
vle8.v v16, (sp)
|
||||
add sp, sp, t0
|
||||
vle8.v v24, (sp)
|
||||
add sp, sp, t0
|
||||
|
||||
LOAD t0, 2 * REGBYTES(sp)
|
||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
vsetvl x0, t0, t1
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
csrw CSR_VSTART, t0
|
||||
LOAD t0, 3 * REGBYTES(sp)
|
||||
csrw CSR_VCSR, t0
|
||||
addi sp, sp, (4 * REGBYTES)
|
||||
|
||||
LOAD t0, 0 * REGBYTES(t2)
|
||||
LOAD t1, 1 * REGBYTES(t2)
|
||||
LOAD t2, 2 * REGBYTES(t2)
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_flen)
|
||||
addi sp, sp, -(2 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
STORE t1, 1 * REGBYTES(sp)
|
||||
_restore_fp_stack:
|
||||
csrr t0, CSR_MSTATUS
|
||||
li t1, MSTATUS_FS_DIRTY
|
||||
and t0,t0,t1
|
||||
bne t0, t1, _restore_done
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
addi sp, sp, (2 * REGBYTES)
|
||||
|
||||
/* Restore fp registers and fcsr and 3 reserved reg space */
|
||||
FPLOAD f0 , 0 * FPREGBYTES(sp)
|
||||
FPLOAD f1 , 1 * FPREGBYTES(sp)
|
||||
FPLOAD f2 , 2 * FPREGBYTES(sp)
|
||||
FPLOAD f3 , 3 * FPREGBYTES(sp)
|
||||
FPLOAD f4 , 4 * FPREGBYTES(sp)
|
||||
FPLOAD f5 , 5 * FPREGBYTES(sp)
|
||||
FPLOAD f6 , 6 * FPREGBYTES(sp)
|
||||
FPLOAD f7 , 7 * FPREGBYTES(sp)
|
||||
FPLOAD f8 , 8 * FPREGBYTES(sp)
|
||||
FPLOAD f9 , 9 * FPREGBYTES(sp)
|
||||
FPLOAD f10, 10 * FPREGBYTES(sp)
|
||||
FPLOAD f11, 11 * FPREGBYTES(sp)
|
||||
FPLOAD f12, 12 * FPREGBYTES(sp)
|
||||
FPLOAD f13, 13 * FPREGBYTES(sp)
|
||||
FPLOAD f14, 14 * FPREGBYTES(sp)
|
||||
FPLOAD f15, 15 * FPREGBYTES(sp)
|
||||
FPLOAD f16, 16 * FPREGBYTES(sp)
|
||||
FPLOAD f17, 17 * FPREGBYTES(sp)
|
||||
FPLOAD f18, 18 * FPREGBYTES(sp)
|
||||
FPLOAD f19, 19 * FPREGBYTES(sp)
|
||||
FPLOAD f20, 20 * FPREGBYTES(sp)
|
||||
FPLOAD f21, 21 * FPREGBYTES(sp)
|
||||
FPLOAD f22, 22 * FPREGBYTES(sp)
|
||||
FPLOAD f23, 23 * FPREGBYTES(sp)
|
||||
FPLOAD f24, 24 * FPREGBYTES(sp)
|
||||
FPLOAD f25, 25 * FPREGBYTES(sp)
|
||||
FPLOAD f26, 26 * FPREGBYTES(sp)
|
||||
FPLOAD f27, 27 * FPREGBYTES(sp)
|
||||
FPLOAD f28, 28 * FPREGBYTES(sp)
|
||||
FPLOAD f29, 29 * FPREGBYTES(sp)
|
||||
FPLOAD f30, 30 * FPREGBYTES(sp)
|
||||
FPLOAD f31, 31 * FPREGBYTES(sp)
|
||||
addi sp, sp, (32 * FPREGBYTES)
|
||||
|
||||
addi sp, sp, -(1 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
LOAD t0, 1 * REGBYTES(sp)
|
||||
csrw CSR_FCSR, t0
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
addi sp, sp, (5 * REGBYTES)
|
||||
#endif
|
||||
|
||||
#if defined(__riscv_flen) || defined(__riscv_vector)
|
||||
addi sp, sp, -(2 * REGBYTES)
|
||||
STORE t0, 0 * REGBYTES(sp)
|
||||
STORE t1, 1 * REGBYTES(sp)
|
||||
_restore_done:
|
||||
LOAD t0, 0 * REGBYTES(sp)
|
||||
LOAD t1, 1 * REGBYTES(sp)
|
||||
addi sp, sp, (2 * REGBYTES)
|
||||
#endif
|
||||
mret
|
||||
|
||||
.size eclic_msip_handler, . - eclic_msip_handler
|
||||
Reference in new issue
Block a user