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/*
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* Copyright (c) 2025 HPMicro
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include "board.h"
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#include "pinmux.h"
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#include "hpm_pmp_drv.h"
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#include "hpm_pllctl_drv.h"
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#include "hpm_clock_drv.h"
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#include "hpm_sysctl_drv.h"
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#include "hpm_pcfg_drv.h"
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#include "hpm_uart_drv.h"
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#include "hpm_gpio_drv.h"
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/**
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* @brief FLASH configuration option definitions:
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* option[0]:
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* [31:16] 0xfcf9 - FLASH configuration option tag
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* [15:4] 0 - Reserved
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* [3:0] option words (exclude option[0])
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* option[1]:
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* [31:28] Flash probe type
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* 0 - SFDP SDR / 1 - SFDP DDR
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* 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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* 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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* 6 - OctaBus DDR (SPI -> OPI DDR)
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* 8 - Xccela DDR (SPI -> OPI DDR)
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* 10 - EcoXiP DDR (SPI -> OPI DDR)
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* [27:24] Command Pads after Power-on Reset
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [23:20] Command Pads after Configuring FLASH
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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* 0 - Not needed
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* 1 - QE bit is at bit 6 in Status Register 1
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* 2 - QE bit is at bit1 in Status Register 2
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* 3 - QE bit is at bit7 in Status Register 2
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* 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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* [15:8] Dummy cycles
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* 0 - Auto-probed / detected / default value
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* Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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* [7:4] Misc.
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* 0 - Not used
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* 1 - SPI mode
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* 2 - Internal loopback
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* 3 - External DQS
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* [3:0] Frequency option
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* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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*
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* option[2] (Effective only if the bit[3:0] in option[0] > 1)
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* [31:20] Reserved
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* [19:16] IO voltage
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* 0 - 3V / 1 - 1.8V
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* [15:12] Pin group
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* 0 - 1st group / 1 - 2nd group
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* [11:8] Connection selection
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* 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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* [7:0] Drive Strength
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* 0 - Default value
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* option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
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* JESD216)
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* [31:16] reserved
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* [15:12] Sector Erase Command Option, not required here
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* [11:8] Sector Size Option, not required here
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* [7:0] Flash Size Option
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* 0 - 4MB / 1 - 8MB / 2 - 16MB
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*/
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#if defined(FLASH_XIP) && FLASH_XIP
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__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000007, 0xE, 0x0};
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#endif
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#if defined(FLASH_UF2) && FLASH_UF2
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ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
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#endif
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/* static function declarations */
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static void board_turnoff_rgb_led(void);
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static void init_uart_pins(UART_Type *ptr);
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static uint32_t board_init_uart_clock(UART_Type *ptr);
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static void init_gpio_pins(void);
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static void init_usb_pins(USB_Type *ptr);
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/* extern function definitions */
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void board_init_clock(void)
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{
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uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
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if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
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/* Configure the External OSC ramp-up time: ~9ms */
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pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U);
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/* Select clock setting preset1 */
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sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
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}
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/* Add clocks to group 0 */
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clock_add_to_group(clock_cpu0, 0);
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clock_add_to_group(clock_mchtmr0, 0);
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clock_add_to_group(clock_axi0, 0);
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clock_add_to_group(clock_axi1, 0);
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clock_add_to_group(clock_axi2, 0);
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clock_add_to_group(clock_ahb, 0);
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clock_add_to_group(clock_xdma, 0);
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clock_add_to_group(clock_hdma, 0);
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clock_add_to_group(clock_xpi0, 0);
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clock_add_to_group(clock_xpi1, 0);
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clock_add_to_group(clock_ram0, 0);
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clock_add_to_group(clock_ram1, 0);
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clock_add_to_group(clock_lmm0, 0);
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clock_add_to_group(clock_lmm1, 0);
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clock_add_to_group(clock_gpio, 0);
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clock_add_to_group(clock_mot0, 0);
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clock_add_to_group(clock_mot1, 0);
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clock_add_to_group(clock_mot2, 0);
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clock_add_to_group(clock_mot3, 0);
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clock_add_to_group(clock_synt, 0);
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clock_add_to_group(clock_ptpc, 0);
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/* Connect Group0 to CPU0 */
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clock_connect_group_to_cpu(0, 0);
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/* Add clocks to Group1 */
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clock_add_to_group(clock_cpu1, 1);
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clock_add_to_group(clock_mchtmr1, 1);
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/* Connect Group1 to CPU1 */
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clock_connect_group_to_cpu(1, 1);
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/* Bump up DCDC voltage to 1275mv */
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pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
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pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG);
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if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
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printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ);
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while (1) {
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}
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}
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clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
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clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
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clock_update_core_clock();
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clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/
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clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
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clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
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}
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void board_init_pmp(void)
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{
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uint32_t start_addr;
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uint32_t end_addr;
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uint32_t length;
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pmp_entry_t pmp_entry[16] = {0};
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uint8_t index = 0;
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/* Init noncachable memory */
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extern uint32_t __noncacheable_start__[];
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extern uint32_t __noncacheable_end__[];
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start_addr = (uint32_t) __noncacheable_start__;
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end_addr = (uint32_t) __noncacheable_end__;
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length = end_addr - start_addr;
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if (length > 0) {
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/* Ensure the address and the length are power of 2 aligned */
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assert((length & (length - 1U)) == 0U);
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assert((start_addr & (length - 1U)) == 0U);
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pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
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pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
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index++;
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}
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/* Init share memory */
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extern uint32_t __share_mem_start__[];
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extern uint32_t __share_mem_end__[];
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start_addr = (uint32_t)__share_mem_start__;
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end_addr = (uint32_t)__share_mem_end__;
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length = end_addr - start_addr;
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if (length > 0) {
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/* Ensure the address and the length are power of 2 aligned */
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assert((length & (length - 1U)) == 0U);
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assert((start_addr & (length - 1U)) == 0U);
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pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
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pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
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index++;
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}
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pmp_config(&pmp_entry[0], index);
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}
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void board_init_console(void)
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{
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uart_config_t config = {0};
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uint32_t freq;
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/* uart needs to configure pin function before enabling clock, otherwise the level change of
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uart rx pin when configuring pin function will cause a wrong data to be received.
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And a uart rx dma request will be generated by default uart fifo dma trigger level. */
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init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
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freq = board_init_uart_clock((UART_Type *)BOARD_CONSOLE_UART_BASE);
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uart_default_config((UART_Type *)BOARD_CONSOLE_UART_BASE, &config);
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config.src_freq_in_hz = freq;
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config.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
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uart_init((UART_Type *)BOARD_CONSOLE_UART_BASE, &config);
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}
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void board_init_gpio_pins(void)
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{
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init_gpio_pins();
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}
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void board_init_led_pins(void)
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{
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board_turnoff_rgb_led();
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init_led_pins_as_gpio();
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gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
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gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
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gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
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}
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void board_init_usb(USB_Type *ptr)
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{
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clock_name_t usb_clk = (ptr == HPM_USB0) ? clock_usb0 : clock_usb1;
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init_usb_pins(ptr);
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clock_add_to_group(usb_clk, 0);
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}
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/* static function definitions */
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static void board_turnoff_rgb_led(void)
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{
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uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(BOARD_LED_OFF_LEVEL);
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HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
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HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
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HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13;
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HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl;
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}
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static void init_uart_pins(UART_Type *ptr)
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{
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if (ptr == HPM_UART0) {
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init_uart0_pins();
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} else if (ptr == HPM_UART2) {
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init_uart2_pins();
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} else if (ptr == HPM_UART13) {
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init_uart13_pins();
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} else if (ptr == HPM_PUART) {
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init_puart_pins();
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}
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}
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static uint32_t board_init_uart_clock(UART_Type *ptr)
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{
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uint32_t freq = 0U;
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if (ptr == HPM_UART0) {
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clock_add_to_group(clock_uart0, 0);
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freq = clock_get_frequency(clock_uart0);
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} else if (ptr == HPM_UART6) {
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clock_add_to_group(clock_uart6, 0);
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freq = clock_get_frequency(clock_uart6);
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} else if (ptr == HPM_UART13) {
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clock_add_to_group(clock_uart13, 0);
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freq = clock_get_frequency(clock_uart13);
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} else if (ptr == HPM_UART14) {
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clock_add_to_group(clock_uart14, 0);
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freq = clock_get_frequency(clock_uart14);
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} else {
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/* Not supported */
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}
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return freq;
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}
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static void init_gpio_pins(void)
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{
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init_gpio_pins_with_pull_up();
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#ifdef USING_GPIO0_FOR_GPIOZ
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init_gpio_pins_using_gpio0();
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#endif
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}
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static void init_usb_pins(USB_Type *ptr)
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{
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if (ptr == HPM_USB0) {
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init_usb0_pins();
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} else if (ptr == HPM_USB1) {
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init_usb1_pins();
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}
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}
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@@ -0,0 +1,22 @@
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set(MCU_VARIANT HPM6750xVMx)
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set(JLINK_DEVICE ${MCU_VARIANT})
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set(JLINK_IF jtag)
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set(HPM_SOC ${SDK_DIR}/soc/HPM6700/HPM6750)
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set(HPM_IP_REGS ${SDK_DIR}/soc/HPM6700/ip)
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set(BOARD_FLASH_SIZE 16M)
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set(BOARD_STACK_SIZE 16K)
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set(BOARD_HEAP_SIZE 16K)
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set(HPM_PLLCTL_DRV_FILE hpm_pllctl_drv.c)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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BOARD_TUD_RHPORT=0
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BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
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BOARD_TUH_RHPORT=1
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BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
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)
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endfunction()
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@@ -0,0 +1,110 @@
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/*
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||||
* Copyright (c) 2021-2025 HPMicro
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||||
*
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||||
* SPDX-License-Identifier: BSD-3-Clause
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*
|
||||
*/
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||||
/* metadata:
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||||
name: HPM6750EVK2
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||||
url: https://hpm-sdk.readthedocs.io/en/v1.6.0/boards/hpm6750evk2/README_en.html
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*/
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#ifndef _HPM_BOARD_H
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#define _HPM_BOARD_H
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#include <stdio.h>
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#include "hpm_common.h"
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#include "hpm_soc.h"
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#include "hpm_soc_feature.h"
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#include "pinmux.h"
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#define BOARD_NAME "hpm6750evk2"
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#ifndef BOARD_RUNNING_CORE
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#define BOARD_RUNNING_CORE HPM_CORE0
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#endif
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#define BOARD_CPU_FREQ (816000000UL)
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/* console section */
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#if BOARD_RUNNING_CORE == HPM_CORE0
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#define BOARD_CONSOLE_UART_BASE HPM_UART0
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#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
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#define BOARD_CONSOLE_UART_IRQ IRQn_UART0
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#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
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#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
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#else
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#define BOARD_CONSOLE_UART_BASE HPM_UART13
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#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13
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#define BOARD_CONSOLE_UART_IRQ IRQn_UART13
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#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX
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#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX
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#endif
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||||
#define BOARD_CONSOLE_UART_BAUDRATE (115200UL)
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/* sdram section */
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||||
#define BOARD_SDRAM_ADDRESS (0x40000000UL)
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#define BOARD_SDRAM_SIZE (32 * SIZE_1MB)
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#define BOARD_SDRAM_CS FEMC_SDRAM_CS0
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||||
#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS
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||||
#define BOARD_SDRAM_COLUMN_ADDR_BITS FEMC_SDRAM_COLUMN_ADDR_9_BITS
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||||
#define BOARD_SDRAM_REFRESH_COUNT (8192UL)
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#define BOARD_SDRAM_REFRESH_IN_MS (64UL)
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||||
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||||
#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL)
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||||
#define BOARD_FLASH_SIZE (16 << 20)
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||||
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||||
/* gpio section */
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||||
#define BOARD_R_GPIO_CTRL HPM_GPIO0
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||||
#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB
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||||
#define BOARD_R_GPIO_PIN 11
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||||
#define BOARD_G_GPIO_CTRL HPM_GPIO0
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||||
#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB
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||||
#define BOARD_G_GPIO_PIN 12
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#define BOARD_B_GPIO_CTRL HPM_GPIO0
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||||
#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB
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||||
#define BOARD_B_GPIO_PIN 13
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||||
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||||
#define BOARD_LED_GPIO_CTRL HPM_GPIO0
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||||
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||||
#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB
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||||
#define BOARD_LED_GPIO_PIN 12
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||||
#define BOARD_LED_OFF_LEVEL 0
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||||
#define BOARD_LED_ON_LEVEL 1
|
||||
|
||||
#define BOARD_LED_TOGGLE_RGB 1
|
||||
|
||||
#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ
|
||||
#define BOARD_APP_GPIO_PIN 2
|
||||
#define BOARD_BUTTON_PRESSED_VALUE 0
|
||||
|
||||
#define USING_GPIO0_FOR_GPIOZ
|
||||
#ifndef USING_GPIO0_FOR_GPIOZ
|
||||
#define BOARD_APP_GPIO_CTRL HPM_BGPIO
|
||||
#define BOARD_APP_GPIO_IRQ IRQn_BGPIO
|
||||
#else
|
||||
#define BOARD_APP_GPIO_CTRL HPM_GPIO0
|
||||
#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
void board_init_clock(void);
|
||||
void board_init_pmp(void);
|
||||
void board_init_console(void);
|
||||
void board_init_gpio_pins(void);
|
||||
void board_init_led_pins(void);
|
||||
void board_init_usb(USB_Type *ptr);
|
||||
void board_print_banner(void);
|
||||
void board_print_clock_freq(void);
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* _HPM_BOARD_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
MCU_VARIANT = HPM6750xVMx
|
||||
JLINK_DEVICE = ${MCU_VARIANT}
|
||||
|
||||
JLINK_IF = jtag
|
||||
|
||||
HPM_SOC = $(SDK_DIR)/soc/HPM6700/HPM6750
|
||||
HPM_IP_REGS = $(SDK_DIR)/soc/HPM6700/ip
|
||||
|
||||
BOARD_FLASH_SIZE = 16M
|
||||
BOARD_STACK_SIZE = 16K
|
||||
BOARD_HEAP_SIZE = 16K
|
||||
|
||||
BOARD_TUD_RHPORT = 0
|
||||
BOARD_TUH_RHPORT = 1
|
||||
|
||||
HPM_PLLCTL_DRV_FILE = hpm_pllctl_drv.c
|
||||
@@ -0,0 +1,862 @@
|
||||
|
||||
/*
|
||||
* Copyright (c) 2025 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*
|
||||
* Automatically generated by HPM Pinmux Tool
|
||||
*
|
||||
*
|
||||
* Note:
|
||||
* PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
|
||||
* besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
|
||||
* expected SoC function can be enabled on these IOs.
|
||||
*/
|
||||
|
||||
#include "pinmux.h"
|
||||
#include "board.h"
|
||||
#include "hpm_trgm_drv.h"
|
||||
|
||||
|
||||
/* PY port IO needs to configure PIOC as well */
|
||||
void init_uart0_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06;
|
||||
}
|
||||
|
||||
void init_uart2_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD;
|
||||
}
|
||||
|
||||
/* PZ port IO needs to configure BIOC as well */
|
||||
void init_uart13_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09;
|
||||
}
|
||||
|
||||
void init_puart_pins(void)
|
||||
{
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_PUART_TXD;
|
||||
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_PUART_RXD;
|
||||
}
|
||||
|
||||
/*
|
||||
* PZ port IO needs to configure BIOC as well.
|
||||
* PZ08 and PZ09 need pull up.
|
||||
* Errata: E00029：IOC PAD_CTL register write restrictions.
|
||||
* When the PE bit is 1, bit [3] must be set to 1,
|
||||
* and DS can only be selected as 0b001 (low drive strength) or 0b110 (high drive strength).
|
||||
*/
|
||||
void init_uart13_pins_as_gpio(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_GPIO_Z_08;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_SOC_PZ_08;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ08].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_GPIO_Z_09;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_SOC_PZ_09;
|
||||
}
|
||||
|
||||
void init_lcd0_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC;
|
||||
|
||||
/* PWM */
|
||||
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10;
|
||||
|
||||
/* RST */
|
||||
HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_GPIO_B_16;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PZ00].FUNC_CTL = IOC_PZ00_FUNC_CTL_GPIO_Z_00;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ00].FUNC_CTL = BIOC_PZ00_FUNC_CTL_SOC_PZ_00;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ00].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Errata: E00029：IOC PAD_CTL register write restrictions.
|
||||
* When the PE bit is 1, bit [3] must be set to 1,
|
||||
* and DS can only be selected as 0b001 (low drive strength) or 0b110 (high drive strength).
|
||||
*/
|
||||
void init_cap_pins(void)
|
||||
{
|
||||
/* CAP_INT */
|
||||
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08;
|
||||
HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(1);
|
||||
|
||||
/* CAP_RST */
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09;
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(1);
|
||||
}
|
||||
|
||||
/* PZ port IO needs to configure BIOC as well */
|
||||
void init_i2c0_pins_as_gpio(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_GPIO_Z_11;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = BIOC_PZ11_FUNC_CTL_SOC_PZ_11;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_GPIO_Z_10;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_SOC_PZ_10;
|
||||
}
|
||||
|
||||
/* PZ port IO needs to configure BIOC as well */
|
||||
void init_i2c0_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = BIOC_PZ11_FUNC_CTL_SOC_PZ_11;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1);
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_SOC_PZ_10;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1);
|
||||
}
|
||||
|
||||
void init_femc_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_FEMC_DQ_16;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_FEMC_DQ_17;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PB31_FUNC_CTL_FEMC_DQ_18;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_FEMC_DQ_30;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_FEMC_DQ_31;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_FEMC_DQ_19;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_FEMC_DQ_20;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_FEMC_DQ_21;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_FEMC_DQ_28;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_FEMC_DQ_29;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_FEMC_DQ_22;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_FEMC_DQ_26;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_FEMC_DQ_27;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_FEMC_DQ_23;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_FEMC_DQ_24;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_FEMC_DQ_25;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_FEMC_DQ_14;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_DQ_15;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_FEMC_DQ_12;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_FEMC_DQ_13;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_DQ_00;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_DQ_10;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_FEMC_DQ_11;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_FEMC_DQ_01;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_FEMC_DQ_08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_FEMC_DQ_09;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_DQ_04;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_FEMC_DQ_03;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_FEMC_DQ_02;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_DQ_07;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_FEMC_DQ_06;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_DQ_05;
|
||||
|
||||
/* SRAM #WE */
|
||||
HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_A_11;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_A_09;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_A_10;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_A_08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_A_07;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_A_06;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_A_01;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_A_00;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_A_05;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_A_04;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_A_03;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_A_02;
|
||||
|
||||
/* SRAM #ADV */
|
||||
HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_BA1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_BA0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_CLK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_CKE;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_CS_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_RAS;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_FEMC_CAS;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_FEMC_WE;
|
||||
|
||||
/* SRAM #LB */
|
||||
HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_DM_0;
|
||||
|
||||
/* SRAM #UB */
|
||||
HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_DM_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_FEMC_DM_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_FEMC_DM_3;
|
||||
|
||||
/* SRAM #CE */
|
||||
HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_FEMC_CS_1;
|
||||
|
||||
/* SRAM #OE */
|
||||
HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_FEMC_A_12;
|
||||
}
|
||||
|
||||
/*
|
||||
* Errata: E00029：IOC PAD_CTL register write restrictions.
|
||||
* When the PE bit is 1, bit [3] must be set to 1,
|
||||
* and DS can only be selected as 0b001 (low drive strength) or 0b110 (high drive strength).
|
||||
*/
|
||||
void init_gpio_pins_with_pull_up(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
|
||||
HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* PZ port IO needs to configure BIOC as well.
|
||||
* Errata: E00029：IOC PAD_CTL register write restrictions.
|
||||
* When the PE bit is 1, bit [3] must be set to 1,
|
||||
* and DS can only be selected as 0b001 (low drive strength) or 0b110 (high drive strength).
|
||||
*/
|
||||
void init_gpio_pins_using_gpio0(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_PZ_02;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Errata: E00029：IOC PAD_CTL register write restrictions.
|
||||
* When the PE bit is 1, bit [3] must be set to 1,
|
||||
* and DS can only be selected as 0b001 (low drive strength) or 0b110 (high drive strength).
|
||||
*/
|
||||
void init_spi2_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_SPI2_CSN;
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI;
|
||||
HPM_IOC->PAD[IOC_PAD_PE30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PE27].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO;
|
||||
HPM_IOC->PAD[IOC_PAD_PE28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08;
|
||||
}
|
||||
|
||||
/*
|
||||
* Errata: E00029：IOC PAD_CTL register write restrictions.
|
||||
* When the PE bit is 1, bit [3] must be set to 1,
|
||||
* and DS can only be selected as 0b001 (low drive strength) or 0b110 (high drive strength).
|
||||
*/
|
||||
void init_spi2_pins_with_gpio_as_cs(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PE27].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO;
|
||||
HPM_IOC->PAD[IOC_PAD_PE28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI;
|
||||
HPM_IOC->PAD[IOC_PAD_PE30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_GPIO_E_31;
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_gptmr3_pins(void)
|
||||
{
|
||||
/* TMR3 compare 1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR3_COMP_1;
|
||||
}
|
||||
|
||||
void init_gptmr4_pins(void)
|
||||
{
|
||||
/* TMR4 capture 1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1;
|
||||
}
|
||||
|
||||
void init_gptmr5_pins(void)
|
||||
{
|
||||
/* TMR5 compare 2 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10;
|
||||
|
||||
/* TMR5 compare 3 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11;
|
||||
|
||||
trgm_output_t trgm2_io_config0 = {0};
|
||||
trgm2_io_config0.invert = 0;
|
||||
trgm2_io_config0.type = trgm_output_same_as_input;
|
||||
trgm2_io_config0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2;
|
||||
trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P10, &trgm2_io_config0);
|
||||
|
||||
trgm_enable_io_output(HPM_TRGM2, 1 << 10);
|
||||
|
||||
trgm_output_t trgm2_io_config1 = {0};
|
||||
trgm2_io_config1.invert = 0;
|
||||
trgm2_io_config1.type = trgm_output_same_as_input;
|
||||
trgm2_io_config1.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3;
|
||||
trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P11, &trgm2_io_config1);
|
||||
|
||||
trgm_enable_io_output(HPM_TRGM2, 1 << 11);
|
||||
}
|
||||
|
||||
void init_hall_trgm_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_TRGM2_P_06;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_TRGM2_P_07;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_TRGM2_P_08;
|
||||
}
|
||||
|
||||
void init_qei_trgm_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_TRGM2_P_09;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10;
|
||||
}
|
||||
|
||||
void init_i2s0_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_I2S0_RXD_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_I2S0_TXD_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK;
|
||||
}
|
||||
|
||||
/* PY port IO needs to configure PIOC */
|
||||
void init_dao_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = PIOC_PY08_FUNC_CTL_SOC_PY_08;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = PIOC_PY09_FUNC_CTL_SOC_PY_09;
|
||||
}
|
||||
|
||||
/* PY port IO needs to configure PIOC */
|
||||
void init_pdm_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_SOC_PY_10;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_SOC_PY_11;
|
||||
}
|
||||
|
||||
void init_vad_pins(void)
|
||||
{
|
||||
HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = PIOC_PY10_FUNC_CTL_VAD_CLK;
|
||||
|
||||
HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = PIOC_PY11_FUNC_CTL_VAD_DAT;
|
||||
}
|
||||
|
||||
void init_cam_pins(void)
|
||||
{
|
||||
/* configure rst pin function, PY port IO needs to configure PIOC */
|
||||
HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK;
|
||||
}
|
||||
|
||||
void init_butn_pins(void)
|
||||
{
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_PBUTN;
|
||||
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = BIOC_PZ03_FUNC_CTL_WBUTN;
|
||||
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_PLED;
|
||||
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_WLED;
|
||||
}
|
||||
|
||||
void init_acmp_pins(void)
|
||||
{
|
||||
/* configure to ACMP_COMP_1(ALT16) function */
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ACMP_COMP_1;
|
||||
|
||||
/* configure to CMP1_INP7 function */
|
||||
HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
|
||||
/* configure to CMP1_INN6 function */
|
||||
HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_enet0_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_GPIO_F_00;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_ETH0_MDIO;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_ETH0_MDC;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_RXD_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_ETH0_RXD_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ETH0_RXD_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_ETH0_RXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_ETH0_RXCK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_ETH0_RXDV;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_ETH0_TXD_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_ETH0_TXD_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_ETH0_TXD_2;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_ETH0_TXD_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_ETH0_TXCK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_ETH0_TXEN;
|
||||
}
|
||||
|
||||
void init_enet1_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPIO_E_26;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_ETH1_REFCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
}
|
||||
|
||||
void init_pwm2_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PWM2_P_5;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PWM2_P_4;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PWM2_P_1;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PWM2_P_0;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PWM2_P_3;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_PWM2_P_2;
|
||||
}
|
||||
|
||||
void init_pwm3_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_PWM3_P_6;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_PWM3_P_7;
|
||||
}
|
||||
|
||||
void init_adc12_pins(void)
|
||||
{
|
||||
/* ADC0.VIN11 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_adc16_pins(void)
|
||||
{
|
||||
/* ADC3.INA2 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_adc_bldc_pins(void)
|
||||
{
|
||||
/* ADC0.VINP7 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
|
||||
/* ADC1.VINP10 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
|
||||
/* ADC2.VINP11 */
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_usb0_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_USB0_ID;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_USB0_OC;
|
||||
}
|
||||
|
||||
void init_usb1_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_USB1_ID;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_USB1_OC;
|
||||
}
|
||||
|
||||
void init_can0_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_CAN0_TXD;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_CAN0_RXD;
|
||||
}
|
||||
|
||||
void init_mcan0_transceiver_phy_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_GPIO_B_14;
|
||||
}
|
||||
|
||||
void init_sdxc1_cmd_pin_enable_1v8_enable_opendrain(void)
|
||||
{
|
||||
/* SDXC1.CMD */
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_SDC1_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1);
|
||||
}
|
||||
|
||||
void init_sdxc1_cmd_pin_enable_1v8_disable_opendrain(void)
|
||||
{
|
||||
/* SDXC1.CMD */
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_SDC1_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(0);
|
||||
}
|
||||
|
||||
void init_sdxc1_cmd_pin_disable_1v8_enable_opendrain(void)
|
||||
{
|
||||
/* SDXC1.CMD */
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_SDC1_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1);
|
||||
}
|
||||
|
||||
void init_sdxc1_cmd_pin_disable_1v8_disable_opendrain(void)
|
||||
{
|
||||
/* SDXC1.CMD */
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_SDC1_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(0);
|
||||
}
|
||||
|
||||
void init_sdxc1_cd_pin(void)
|
||||
{
|
||||
/* SDXC1.CDN */
|
||||
HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15;
|
||||
HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_sdxc1_clk_data_pins_enable_1v8(void)
|
||||
{
|
||||
/* SDXC1.CLK */
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_SDC1_CLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA0 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_SDC1_DATA_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_sdxc1_clk_data_pins_disable_1v8(void)
|
||||
{
|
||||
/* SDXC1.CLK */
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_SDC1_CLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA0 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_SDC1_DATA_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_sdxc1_clk_data_pins_width4_enable_1v8(void)
|
||||
{
|
||||
/* SDXC1.DATA1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_SDC1_DATA_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA2 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_SDC1_DATA_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA3 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_SDC1_DATA_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.CLK */
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_SDC1_CLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA0 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_SDC1_DATA_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_sdxc1_clk_data_pins_width4_disable_1v8(void)
|
||||
{
|
||||
/* SDXC1.DATA1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_SDC1_DATA_1;
|
||||
HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA2 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_SDC1_DATA_2;
|
||||
HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA3 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_SDC1_DATA_3;
|
||||
HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.CLK */
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_SDC1_CLK;
|
||||
HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
/* SDXC1.DATA0 */
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_SDC1_DATA_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = IOC_PAD_PAD_CTL_MS_SET(0) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_sdxc1_pwr_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_GPIO_C_20;
|
||||
HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_clk_obs_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0;
|
||||
}
|
||||
|
||||
void init_rgb_pwm_pins(void)
|
||||
{
|
||||
/* Red */
|
||||
HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_TRGM1_P_01;
|
||||
|
||||
/* Green */
|
||||
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_TRGM0_P_06;
|
||||
|
||||
/* BLUE */
|
||||
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_TRGM1_P_03;
|
||||
}
|
||||
|
||||
void init_led_pins_as_gpio(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13;
|
||||
}
|
||||
|
||||
void init_enet_pps_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0;
|
||||
}
|
||||
|
||||
void init_enet_pps_capture_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ETH0_EVTI_1;
|
||||
}
|
||||
|
||||
void init_tamper_pins(void)
|
||||
{
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_TAMP_08 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_TAMP_09;
|
||||
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_TAMP_10;
|
||||
}
|
||||
|
||||
/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
|
||||
void init_uart_break_signal_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_GPIO_E_31;
|
||||
HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | 0x08 | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
}
|
||||
|
||||
void init_gptmr3_channel_pin_as_output(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR3_COMP_1;
|
||||
}
|
||||
|
||||
void init_gptmr4_channel_pin_as_capture(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1;
|
||||
}
|
||||
|
||||
void init_gptmr5_channel2_pin_as_output(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10;
|
||||
|
||||
trgm_output_t trgm2_io_config0 = {0};
|
||||
trgm2_io_config0.invert = 0;
|
||||
trgm2_io_config0.type = trgm_output_same_as_input;
|
||||
trgm2_io_config0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2;
|
||||
trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P10, &trgm2_io_config0);
|
||||
|
||||
trgm_enable_io_output(HPM_TRGM2, 1 << 10);
|
||||
}
|
||||
|
||||
void init_gptmr5_channel3_pin_as_output(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11;
|
||||
|
||||
trgm_output_t trgm2_io_config0 = {0};
|
||||
trgm2_io_config0.invert = 0;
|
||||
trgm2_io_config0.type = trgm_output_same_as_input;
|
||||
trgm2_io_config0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3;
|
||||
trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P11, &trgm2_io_config0);
|
||||
|
||||
trgm_enable_io_output(HPM_TRGM2, 1 << 11);
|
||||
}
|
||||
|
||||
void init_clk_ref_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_SOC_REF1;
|
||||
}
|
||||
|
||||
void init_brownout_indicate_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_GPIO_E_30;
|
||||
}
|
||||
|
||||
void board_init_i2c_eeprom_pin(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = BIOC_PZ11_FUNC_CTL_SOC_PZ_11;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1);
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_SOC_PZ_10;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1);
|
||||
}
|
||||
@@ -0,0 +1,89 @@
|
||||
|
||||
/*
|
||||
* Copyright (c) 2025 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*
|
||||
* Automatically generated by HPM Pinmux Tool
|
||||
*
|
||||
*
|
||||
* Note:
|
||||
* PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
|
||||
* besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
|
||||
* expected SoC function can be enabled on these IOs.
|
||||
*/
|
||||
|
||||
#ifndef HPM_PINMUX_H
|
||||
#define HPM_PINMUX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void init_uart0_pins(void);
|
||||
void init_uart2_pins(void);
|
||||
void init_uart13_pins(void);
|
||||
void init_puart_pins(void);
|
||||
void init_uart13_pins_as_gpio(void);
|
||||
void init_lcd0_pins(void);
|
||||
void init_cap_pins(void);
|
||||
void init_i2c0_pins_as_gpio(void);
|
||||
void init_i2c0_pins(void);
|
||||
void init_femc_pins(void);
|
||||
void init_gpio_pins_with_pull_up(void);
|
||||
void init_gpio_pins_using_gpio0(void);
|
||||
void init_spi2_pins(void);
|
||||
void init_spi2_pins_with_gpio_as_cs(void);
|
||||
void init_gptmr3_pins(void);
|
||||
void init_gptmr4_pins(void);
|
||||
void init_gptmr5_pins(void);
|
||||
void init_hall_trgm_pins(void);
|
||||
void init_qei_trgm_pins(void);
|
||||
void init_i2s0_pins(void);
|
||||
void init_dao_pins(void);
|
||||
void init_pdm_pins(void);
|
||||
void init_vad_pins(void);
|
||||
void init_cam_pins(void);
|
||||
void init_butn_pins(void);
|
||||
void init_acmp_pins(void);
|
||||
void init_enet0_pins(void);
|
||||
void init_enet1_pins(void);
|
||||
void init_pwm2_pins(void);
|
||||
void init_pwm3_pins(void);
|
||||
void init_adc12_pins(void);
|
||||
void init_adc16_pins(void);
|
||||
void init_adc_bldc_pins(void);
|
||||
void init_usb0_pins(void);
|
||||
void init_usb1_pins(void);
|
||||
void init_can0_pins(void);
|
||||
void init_mcan0_transceiver_phy_pin(void);
|
||||
void init_sdxc1_cmd_pin_enable_1v8_enable_opendrain(void);
|
||||
void init_sdxc1_cmd_pin_enable_1v8_disable_opendrain(void);
|
||||
void init_sdxc1_cmd_pin_disable_1v8_enable_opendrain(void);
|
||||
void init_sdxc1_cmd_pin_disable_1v8_disable_opendrain(void);
|
||||
void init_sdxc1_cd_pin(void);
|
||||
void init_sdxc1_clk_data_pins_enable_1v8(void);
|
||||
void init_sdxc1_clk_data_pins_disable_1v8(void);
|
||||
void init_sdxc1_clk_data_pins_width4_enable_1v8(void);
|
||||
void init_sdxc1_clk_data_pins_width4_disable_1v8(void);
|
||||
void init_sdxc1_pwr_pin(void);
|
||||
void init_clk_obs_pins(void);
|
||||
void init_rgb_pwm_pins(void);
|
||||
void init_led_pins_as_gpio(void);
|
||||
void init_enet_pps_pins(void);
|
||||
void init_enet_pps_capture_pins(void);
|
||||
void init_tamper_pins(void);
|
||||
void init_uart_break_signal_pin(void);
|
||||
void init_gptmr3_channel_pin_as_output(void);
|
||||
void init_gptmr4_channel_pin_as_capture(void);
|
||||
void init_gptmr5_channel2_pin_as_output(void);
|
||||
void init_gptmr5_channel3_pin_as_output(void);
|
||||
void init_clk_ref_pin(void);
|
||||
void init_brownout_indicate_pin(void);
|
||||
void board_init_i2c_eeprom_pin(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPM_PINMUX_H */
|
||||
Reference in new issue
Block a user