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/*
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* Copyright (c) 2025 HPMicro
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include "board.h"
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#include "pinmux.h"
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#include "hpm_pmp_drv.h"
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#include "hpm_pllctl_drv.h"
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#include "hpm_clock_drv.h"
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#include "hpm_sysctl_drv.h"
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#include "hpm_pcfg_drv.h"
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#include "hpm_uart_drv.h"
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#include "hpm_gpio_drv.h"
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/**
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* @brief FLASH configuration option definitions:
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* option[0]:
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* [31:16] 0xfcf9 - FLASH configuration option tag
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* [15:4] 0 - Reserved
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* [3:0] option words (exclude option[0])
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* option[1]:
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* [31:28] Flash probe type
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* 0 - SFDP SDR / 1 - SFDP DDR
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* 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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* 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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* 6 - OctaBus DDR (SPI -> OPI DDR)
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* 8 - Xccela DDR (SPI -> OPI DDR)
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* 10 - EcoXiP DDR (SPI -> OPI DDR)
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* [27:24] Command Pads after Power-on Reset
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [23:20] Command Pads after Configuring FLASH
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* 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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* [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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* 0 - Not needed
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* 1 - QE bit is at bit 6 in Status Register 1
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* 2 - QE bit is at bit1 in Status Register 2
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* 3 - QE bit is at bit7 in Status Register 2
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* 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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* [15:8] Dummy cycles
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* 0 - Auto-probed / detected / default value
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* Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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* [7:4] Misc.
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* 0 - Not used
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* 1 - SPI mode
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* 2 - Internal loopback
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* 3 - External DQS
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* [3:0] Frequency option
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* 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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*
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* option[2] (Effective only if the bit[3:0] in option[0] > 1)
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* [31:20] Reserved
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* [19:16] IO voltage
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* 0 - 3V / 1 - 1.8V
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* [15:12] Pin group
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* 0 - 1st group / 1 - 2nd group
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* [11:8] Connection selection
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* 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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* [7:0] Drive Strength
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* 0 - Default value
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* option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
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* JESD216)
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* [31:16] reserved
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* [15:12] Sector Erase Command Option, not required here
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* [11:8] Sector Size Option, not required here
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* [7:0] Flash Size Option
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* 0 - 4MB / 1 - 8MB / 2 - 16MB
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*/
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#if defined(FLASH_XIP) && FLASH_XIP
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__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000007, 0xE, 0x0};
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#endif
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#if defined(FLASH_UF2) && FLASH_UF2
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ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
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#endif
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/* static function declarations */
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static void board_turnoff_rgb_led(void);
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static void init_uart_pins(UART_Type *ptr);
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static uint32_t board_init_uart_clock(UART_Type *ptr);
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static void init_gpio_pins(void);
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static void init_usb_pins(USB_Type *ptr);
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/* extern function definitions */
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void board_init_clock(void)
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{
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uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
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if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
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/* Configure the External OSC ramp-up time: ~9ms */
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pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U);
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/* Select clock setting preset1 */
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sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1);
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}
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/* Add clocks to group 0 */
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clock_add_to_group(clock_cpu0, 0);
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clock_add_to_group(clock_mchtmr0, 0);
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clock_add_to_group(clock_axi0, 0);
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clock_add_to_group(clock_axi1, 0);
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clock_add_to_group(clock_axi2, 0);
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clock_add_to_group(clock_ahb, 0);
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clock_add_to_group(clock_xdma, 0);
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clock_add_to_group(clock_hdma, 0);
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clock_add_to_group(clock_xpi0, 0);
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clock_add_to_group(clock_xpi1, 0);
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clock_add_to_group(clock_ram0, 0);
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clock_add_to_group(clock_ram1, 0);
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clock_add_to_group(clock_lmm0, 0);
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clock_add_to_group(clock_lmm1, 0);
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clock_add_to_group(clock_gpio, 0);
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clock_add_to_group(clock_mot0, 0);
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clock_add_to_group(clock_mot1, 0);
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clock_add_to_group(clock_mot2, 0);
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clock_add_to_group(clock_mot3, 0);
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clock_add_to_group(clock_synt, 0);
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clock_add_to_group(clock_ptpc, 0);
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/* Connect Group0 to CPU0 */
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clock_connect_group_to_cpu(0, 0);
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/* Add clocks to Group1 */
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clock_add_to_group(clock_cpu1, 1);
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clock_add_to_group(clock_mchtmr1, 1);
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/* Connect Group1 to CPU1 */
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clock_connect_group_to_cpu(1, 1);
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/* Bump up DCDC voltage to 1275mv */
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pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
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pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG);
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if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
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printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ);
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while (1) {
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}
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}
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clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
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clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
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clock_update_core_clock();
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clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/
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clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
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clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
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}
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void board_init_pmp(void)
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{
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uint32_t start_addr;
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uint32_t end_addr;
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uint32_t length;
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pmp_entry_t pmp_entry[16] = {0};
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uint8_t index = 0;
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/* Init noncachable memory */
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extern uint32_t __noncacheable_start__[];
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extern uint32_t __noncacheable_end__[];
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start_addr = (uint32_t) __noncacheable_start__;
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end_addr = (uint32_t) __noncacheable_end__;
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length = end_addr - start_addr;
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if (length > 0) {
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/* Ensure the address and the length are power of 2 aligned */
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assert((length & (length - 1U)) == 0U);
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assert((start_addr & (length - 1U)) == 0U);
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pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
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pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
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index++;
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}
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/* Init share memory */
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extern uint32_t __share_mem_start__[];
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extern uint32_t __share_mem_end__[];
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start_addr = (uint32_t)__share_mem_start__;
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end_addr = (uint32_t)__share_mem_end__;
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length = end_addr - start_addr;
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if (length > 0) {
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/* Ensure the address and the length are power of 2 aligned */
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assert((length & (length - 1U)) == 0U);
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assert((start_addr & (length - 1U)) == 0U);
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pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
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pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
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pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
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index++;
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}
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pmp_config(&pmp_entry[0], index);
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}
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void board_init_console(void)
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{
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uart_config_t config = {0};
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uint32_t freq;
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/* uart needs to configure pin function before enabling clock, otherwise the level change of
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uart rx pin when configuring pin function will cause a wrong data to be received.
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And a uart rx dma request will be generated by default uart fifo dma trigger level. */
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init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
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freq = board_init_uart_clock((UART_Type *)BOARD_CONSOLE_UART_BASE);
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uart_default_config((UART_Type *)BOARD_CONSOLE_UART_BASE, &config);
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config.src_freq_in_hz = freq;
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config.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
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uart_init((UART_Type *)BOARD_CONSOLE_UART_BASE, &config);
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}
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void board_init_gpio_pins(void)
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{
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init_gpio_pins();
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}
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void board_init_led_pins(void)
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{
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board_turnoff_rgb_led();
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init_led_pins_as_gpio();
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gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
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gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
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gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
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}
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void board_init_usb(USB_Type *ptr)
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{
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clock_name_t usb_clk = (ptr == HPM_USB0) ? clock_usb0 : clock_usb1;
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init_usb_pins(ptr);
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clock_add_to_group(usb_clk, 0);
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}
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/* static function definitions */
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static void board_turnoff_rgb_led(void)
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{
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uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(BOARD_LED_OFF_LEVEL);
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HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11;
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HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12;
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HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13;
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HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl;
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HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl;
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}
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static void init_uart_pins(UART_Type *ptr)
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{
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if (ptr == HPM_UART0) {
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init_uart0_pins();
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} else if (ptr == HPM_UART2) {
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init_uart2_pins();
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} else if (ptr == HPM_UART13) {
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init_uart13_pins();
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} else if (ptr == HPM_PUART) {
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init_puart_pins();
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}
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}
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static uint32_t board_init_uart_clock(UART_Type *ptr)
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{
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uint32_t freq = 0U;
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if (ptr == HPM_UART0) {
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clock_add_to_group(clock_uart0, 0);
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freq = clock_get_frequency(clock_uart0);
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} else if (ptr == HPM_UART6) {
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clock_add_to_group(clock_uart6, 0);
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freq = clock_get_frequency(clock_uart6);
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} else if (ptr == HPM_UART13) {
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clock_add_to_group(clock_uart13, 0);
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freq = clock_get_frequency(clock_uart13);
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} else if (ptr == HPM_UART14) {
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clock_add_to_group(clock_uart14, 0);
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freq = clock_get_frequency(clock_uart14);
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} else {
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/* Not supported */
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}
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return freq;
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}
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static void init_gpio_pins(void)
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{
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init_gpio_pins_with_pull_up();
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#ifdef USING_GPIO0_FOR_GPIOZ
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init_gpio_pins_using_gpio0();
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#endif
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}
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static void init_usb_pins(USB_Type *ptr)
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{
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if (ptr == HPM_USB0) {
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init_usb0_pins();
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} else if (ptr == HPM_USB1) {
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init_usb1_pins();
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}
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}
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