initial commit

2026-10-11 21:48:59 +08:00
commit b44ce7bd77
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
@@ -0,0 +1,19 @@
+set(MCU_VARIANT LPC54114)
+set(MCU_CORE LPC54114_cm4)
+
+set(JLINK_DEVICE LPC54114J256_M4)
+set(PYOCD_TARGET LPC54114)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54114J256_cm4_flash.ld)
+
+# Only Port 0 Full-Speed
+set(RHPORT_DEVICE 0)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54114J256BD64_cm4
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_cm4_hardabi.a
+    )
+endfunction()
@@ -0,0 +1,76 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: LPCXpresso54114
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54114-board:OM13089
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN     0x80u   // Enables digital function
+#define IOCON_PIO_FUNC0          0x00u
+#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
+#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF    0x0100u // Input filter disabled
+#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
+#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
+#define IOCON_PIO_MODE_PULLUP    0x10u
+#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
+
+// LED
+#define LED_PORT              0
+#define LED_PIN               29
+#define LED_STATE_ON          0
+
+// WAKE button
+#define BUTTON_PORT           0
+#define BUTTON_PIN            24
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 0, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 1, IOCON_PIO_DIG_FUNC1_EN
+
+// USB0 VBUS
+#define USB0_VBUS_PINMUX      1, 6, IOCON_PIO_DIG_FUNC7_EN
+
+// XTAL
+//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
@@ -0,0 +1,13 @@
+MCU_VARIANT = LPC54114
+MCU_CORE = LPC54114_cm4
+
+CFLAGS += -DCPU_LPC54114J256BD64_cm4
+LD_FILE = $(MCU_DIR)/gcc/LPC54114J256_cm4_flash.ld
+
+LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_cm4_hardabi.a
+
+JLINK_DEVICE = LPC54114J256_M4
+PYOCD_TARGET = LPC54114
+
+# flash using pyocd
+flash: flash-pyocd
@@ -0,0 +1,25 @@
+set(MCU_VARIANT LPC54608)
+set(MCU_CORE LPC54608)
+
+set(JLINK_DEVICE LPC54608J512)
+set(PYOCD_TARGET LPC54608)
+set(NXPLINK_DEVICE LPC54608:LPCXpresso54608)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54608J512_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54608J512ET180
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a
+    )
+endfunction()
@@ -0,0 +1,85 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: LPCXpresso54608
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-development-board-for-lpc5460x-mcus:OM13092
+*/
+
+#ifndef BOARD_LPCXPRESSO54608_H_
+#define BOARD_LPCXPRESSO54608_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN     0x0100u   // Enables digital function
+#define IOCON_PIO_FUNC0          0x00u
+#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
+#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF    0x0200u // Input filter disabled
+#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
+#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
+#define IOCON_PIO_MODE_PULLUP    0x10u
+#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
+
+// LED
+#define LED_PORT              2
+#define LED_PIN               2
+#define LED_STATE_ON          0
+
+// WAKE button
+#define BUTTON_PORT           1
+#define BUTTON_PIN            1
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
+
+// USB0 VBUS
+#define USB0_VBUS_PINMUX      0, 22, IOCON_PIO_DIG_FUNC7_EN
+
+// Power switch
+#define USBFS_POWER_PORT      4
+#define USBFS_POWER_PIN       7
+#define USBFS_POWER_STATE_ON  0
+
+#define USBHS_POWER_PORT      4
+#define USBHS_POWER_PIN       9
+#define USBHS_POWER_STATE_ON  0
+
+// XTAL
+//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
@@ -0,0 +1,18 @@
+MCU_VARIANT = LPC54608
+MCU_CORE = LPC54608
+
+PORT ?= 1
+
+CFLAGS += -DCPU_LPC54608J512ET180
+CFLAGS += -Wno-error=double-promotion
+
+LD_FILE = $(MCU_DIR)/gcc/LPC54608J512_flash.ld
+
+LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
+
+JLINK_DEVICE = LPC54608J512
+PYOCD_TARGET = LPC54608
+
+#flash: flash-pyocd
+
+flash: flash-jlink
@@ -0,0 +1,25 @@
+set(MCU_VARIANT LPC54628)
+set(MCU_CORE LPC54628)
+
+set(JLINK_DEVICE LPC54628J512)
+set(PYOCD_TARGET LPC54628)
+set(NXPLINK_DEVICE LPC54628:LPCXpresso54628)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54628J512ET180
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a
+    )
+endfunction()
@@ -0,0 +1,76 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: LPCXpresso54628
+   url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54628-development-board:OM13098
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN     0x0100u   // Enables digital function
+#define IOCON_PIO_FUNC0          0x00u
+#define IOCON_PIO_FUNC1          0x01u   // Selects pin function 1
+#define IOCON_PIO_FUNC7          0x07u   // Selects pin function 7
+#define IOCON_PIO_INPFILT_OFF    0x0200u // Input filter disabled
+#define IOCON_PIO_INV_DI         0x00u   // Input function is not inverted
+#define IOCON_PIO_MODE_INACT     0x00u   // No addition pin function
+#define IOCON_PIO_MODE_PULLUP    0x10u
+#define IOCON_PIO_OPENDRAIN_DI   0x00u   // Open drain is disabled
+#define IOCON_PIO_SLEW_STANDARD  0x00u   // Standard mode, output slew rate control is enabled
+
+// LED
+#define LED_PORT              2
+#define LED_PIN               2
+#define LED_STATE_ON          0
+
+// WAKE button
+#define BUTTON_PORT           1
+#define BUTTON_PIN            1
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
+
+// USB0 VBUS
+#define USB0_VBUS_PINMUX      0, 22, IOCON_PIO_DIG_FUNC7_EN
+
+// XTAL
+//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
@@ -0,0 +1,18 @@
+MCU_VARIANT = LPC54628
+MCU_CORE = LPC54628
+
+PORT ?= 1
+
+CFLAGS += -DCPU_LPC54628J512ET180
+CFLAGS += -Wno-error=double-promotion
+
+LD_FILE = $(MCU_DIR)/gcc/LPC54628J512_flash.ld
+
+LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
+
+JLINK_DEVICE = LPC54628J512
+PYOCD_TARGET = LPC54628
+
+#flash: flash-pyocd
+
+flash: flash-jlink
@@ -0,0 +1,280 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: NXP
+*/
+
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_power.h"
+#include "fsl_iocon.h"
+#include "fsl_usart.h"
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+// Digital pin function n enabled
+#define IOCON_PIO_DIG_FUNC0_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC0)
+#define IOCON_PIO_DIG_FUNC1_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC1)
+#define IOCON_PIO_DIG_FUNC4_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC4)
+#define IOCON_PIO_DIG_FUNC7_EN   (IOCON_PIO_DIGITAL_EN | IOCON_PIO_INPFILT_OFF | IOCON_PIO_FUNC7)
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void) {
+  tusb_int_handler(0, true);
+}
+
+void USB1_IRQHandler(void) {
+  tusb_int_handler(1, true);
+}
+
+/****************************************************************
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: SYSTICK_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+******************************************************************/
+void BootClockFROHF96M(void) {
+  /*!< Set up the clock sources */
+  /*!< Set up FRO */
+  POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+
+  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+  /*!< Set up dividers */
+  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
+
+  /*!< Set up clock selectors - Attach clocks to the peripheries */
+  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+
+  /*!< Set SystemCoreClock variable. */
+  SystemCoreClock = 96000000U;
+}
+
+void board_init(void) {
+  // Enable IOCON clock
+  CLOCK_EnableClock(kCLOCK_Iocon);
+
+  // Init 96 MHz clock
+  BootClockFROHF96M();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR from running before scheduler start
+  SysTick->CTRL &= ~1U;
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  // Init all GPIO ports 54114 only has 2 ports.
+  GPIO_PortInit(GPIO, LED_PORT);
+  GPIO_PortInit(GPIO, BUTTON_PORT);
+
+  // LED
+  IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN);
+  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 0};
+  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
+
+  board_led_write(0);
+
+  // Button
+  IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN | IOCON_PIO_MODE_PULLUP);
+  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
+
+#ifdef UART_DEV
+  // UART
+  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
+  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
+
+  // Enable UART when debug log is on
+  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+  usart_config_t uart_config;
+  USART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx     = true;
+  uart_config.enableRx     = true;
+  USART_Init(UART_DEV, &uart_config, 12000000);
+#endif
+
+#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
+  // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports
+  #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
+    /* PORT0 PIN22 configured as USB0_VBUS */
+    IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
+
+    // Port0 is Full Speed
+    POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
+    CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+
+    if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) {
+      /*According to reference manual, device mode setting has to be set by access usb host register */
+      CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
+      USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
+      CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
+
+      CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+    } else {
+    #ifdef USBFS_POWER_PORT
+      /* Configure USB0 Power Switch Pin */
+      IOCON_PinMuxSet(IOCON, USBFS_POWER_PORT, USBFS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN);
+
+      gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBFS_POWER_STATE_ON};
+      GPIO_PinInit(GPIO, USBFS_POWER_PORT, USBFS_POWER_PIN, &power_pin_config);
+    #endif
+      CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
+      USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK;
+    }
+  #endif
+
+ #if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
+  // Port1 is High Speed
+
+  /* Turn on USB1 Phy */
+  POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
+
+  /* reset the IP to make sure it's in reset state. */
+  RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
+
+  if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) {
+    /* According to reference manual, device mode setting has to be set by access usb host register */
+    CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
+
+    USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
+    USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+
+    CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
+    /* enable USB Device clock */
+    CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUsbPll, 0U);
+  } else {
+  #ifdef USBHS_POWER_PORT
+    /* Configure USB1 Power Switch Pin */
+    IOCON_PinMuxSet(IOCON, USBHS_POWER_PORT, USBHS_POWER_PIN, IOCON_PIO_DIG_FUNC0_EN);
+
+    gpio_pin_config_t const power_pin_config = {kGPIO_DigitalOutput, USBHS_POWER_STATE_ON};
+    GPIO_PinInit(GPIO, USBHS_POWER_PORT, USBHS_POWER_PIN, &power_pin_config);
+  #endif
+    CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 0U);
+  }
+  #endif
+#else
+  IOCON_PinMuxSet(IOCON, USB0_VBUS_PINMUX);
+  // LPC5411x series only has full speed device
+  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); // Turn on USB Phy
+  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  // active low
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return -1;
+}
+
+int board_uart_write(void const* buf, int len) {
+#ifdef UART_DEV
+  const uint8_t *p = (const uint8_t *) buf;
+  int count = 0;
+  while (count < len) {
+    if (UART_DEV->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) {
+      UART_DEV->FIFOWR = p[count];
+      count++;
+    } else {
+      break;
+    }
+  }
+  return count;
+#else
+  (void) buf;
+  (void) len;
+  return -1;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t tusb_time_millis_api(void) {
+  return system_ticks;
+}
+#endif
+
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  (void) __status;
+  while (1) {}
+}
+#endif
+
+#endif
@@ -0,0 +1,176 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC54 CACHE INTERNAL "")
+
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+
+# default device port to USB1 highspeed, host to USB0 fullspeed
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 1)
+endif ()
+
+# port 0 is fullspeed, port 1 is highspeed
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+#------------------------------------
+# Startup & Linker script
+#------------------------------------
+if (NOT DEFINED LD_FILE_GNU)
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+endif ()
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+if (NOT DEFINED STARTUP_FILE_GNU)
+set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+endif ()
+set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+if (NOT DEFINED LD_FILE_IAR)
+  set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/${MCU_CORE}_flash.icf)
+endif ()
+
+if (NOT DEFINED STARTUP_FILE_IAR)
+  set(STARTUP_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/iar/startup_${MCU_CORE}.s)
+endif ()
+
+#------------------------------------
+# Board Target
+#------------------------------------
+function(family_add_board BOARD_TARGET)
+  add_library(${BOARD_TARGET} STATIC
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/flexcomm/usart
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+    __STARTUP_CLEAR_BSS
+    )
+
+ # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+  if (RHPORT_DEVICE EQUAL 1)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      [=[CFG_TUD_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
+      )
+  endif ()
+  if (RHPORT_HOST EQUAL 1)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      [=[CFG_TUH_MEM_SECTION=__attribute__((section("m_usb_global")))]=]
+      CFG_TUH_USBIP_IP3516=1
+      )
+  endif ()
+
+  update_board(${BOARD_TARGET})
+endfunction()
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC54)
+
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  if (RHPORT_HOST EQUAL 0)
+    target_sources(${TARGET} PUBLIC
+      ${TOP}/src/portable/ohci/ohci.c
+      )
+  elseif (RHPORT_HOST EQUAL 1)
+    target_sources(${TARGET} PUBLIC
+      ${TOP}/src/portable/nxp/lpc_ip3516/hcd_lpc_ip3516.c
+      )
+  endif ()
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      "LINKER:--defsym=__stack_size__=0x1000"
+      "LINKER:--defsym=__heap_size__=0"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      "LINKER:--config_def=__stack_size__=0x1000"
+      "LINKER:--config_def=__heap_size__=0"
+      )
+  endif ()
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
+  endif ()
+  set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
+    SKIP_LINTING ON
+    COMPILE_OPTIONS -w)
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
@@ -0,0 +1,52 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
+
+CFLAGS += \
+  -flto \
+  -D__STARTUP_CLEAR_BSS \
+  -DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
+
+ifeq ($(PORT), 1)
+  $(info "PORT1 High Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+  CFLAGS += -DBOARD_TUD_RHPORT=1
+  # LPC55 Highspeed Port1 can only write to USB_SRAM region
+  CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
+else
+  $(info "PORT0 Full Speed")
+endif
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter
+
+LDFLAGS += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs
+
+SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+	$(MCU_DIR)/system_$(MCU_CORE).c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(MCU_DIR)/drivers/fsl_power.c \
+	$(MCU_DIR)/drivers/fsl_reset.c \
+	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
+	$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
+	$(SDK_DIR)/drivers/common/fsl_common_arm.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
+	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
+	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
+
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
@@ -0,0 +1,84 @@
+/*
+** ###################################################################
+**     Processors:          LPC54608J512BD208
+**                          LPC54608J512ET180
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    LPC546xx User manual Rev.1.9  5 June 2017
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b241125
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x000003FF;
+
+define symbol m_text_start             = 0x00000400;
+define symbol m_text_end               = 0x0007FFFF;
+
+define symbol m_data_start             = 0x20000000;
+define symbol m_data_end               = 0x20027FFF;
+
+define symbol m_usb_sram_start         = 0x40100000;
+define symbol m_usb_sram_end           = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size             = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region                     { section m_usb_bdt };
+place in USB_SRAM_region                    { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  /* Required in a multi-threaded application */
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in CSTACK_region                      { block CSTACK };
@@ -0,0 +1,82 @@
+/*
+** ###################################################################
+**     Processor:           LPC54628J512ET180
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    LPC546xx User manual Rev.1.9  5 June 2017
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b241125
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2024 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x000003FF;
+
+define symbol m_text_start             = 0x00000400;
+define symbol m_text_end               = 0x0007FFFF;
+
+define symbol m_data_start             = 0x20000000;
+define symbol m_data_end               = 0x20027FFF;
+
+define symbol m_usb_sram_start         = 0x40100000;
+define symbol m_usb_sram_end           = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size             = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region                     { section m_usb_bdt };
+place in USB_SRAM_region                    { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  /* Required in a multi-threaded application */
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in CSTACK_region                      { block CSTACK };
@@ -0,0 +1,654 @@
+; -------------------------------------------------------------------------
+;  @file:    startup_LPC54608.s
+;  @purpose: CMSIS Cortex-M4 Core Device Startup File
+;            LPC54608
+;  @version: 2.0
+;  @date:    2024-10-29
+;  @build:   b250521
+; -------------------------------------------------------------------------
+;
+; Copyright 1997-2016 Freescale Semiconductor, Inc.
+; Copyright 2016-2025 NXP
+; SPDX-License-Identifier: BSD-3-Clause
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__iar_init$$done:              ; The vector table is not needed
+                      ; until after copy initialization is done
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     MemManage_Handler                             ;MPU Fault Handler
+        DCD     BusFault_Handler                              ;Bus Fault Handler
+        DCD     UsageFault_Handler                            ;Usage Fault Handler
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0xFFFFFFFF                                    ;ECRP
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     DebugMon_Handler                              ;Debug Monitor Handler
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     WDT_BOD_IRQHandler                            ;Windowed watchdog timer, Brownout detect
+        DCD     DMA0_IRQHandler                               ;DMA controller
+        DCD     GINT0_IRQHandler                              ;GPIO group 0
+        DCD     GINT1_IRQHandler                              ;GPIO group 1
+        DCD     PIN_INT0_IRQHandler                           ;Pin interrupt 0 or pattern match engine slice 0
+        DCD     PIN_INT1_IRQHandler                           ;Pin interrupt 1or pattern match engine slice 1
+        DCD     PIN_INT2_IRQHandler                           ;Pin interrupt 2 or pattern match engine slice 2
+        DCD     PIN_INT3_IRQHandler                           ;Pin interrupt 3 or pattern match engine slice 3
+        DCD     UTICK0_IRQHandler                             ;Micro-tick Timer
+        DCD     MRT0_IRQHandler                               ;Multi-rate timer
+        DCD     CTIMER0_IRQHandler                            ;Standard counter/timer CTIMER0
+        DCD     CTIMER1_IRQHandler                            ;Standard counter/timer CTIMER1
+        DCD     SCT0_IRQHandler                               ;SCTimer/PWM
+        DCD     CTIMER3_IRQHandler                            ;Standard counter/timer CTIMER3
+        DCD     FLEXCOMM0_IRQHandler                          ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM1_IRQHandler                          ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM2_IRQHandler                          ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM3_IRQHandler                          ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM4_IRQHandler                          ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM5_IRQHandler                          ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+        DCD     FLEXCOMM6_IRQHandler                          ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     FLEXCOMM7_IRQHandler                          ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     ADC0_SEQA_IRQHandler                          ;ADC0 sequence A completion.
+        DCD     ADC0_SEQB_IRQHandler                          ;ADC0 sequence B completion.
+        DCD     ADC0_THCMP_IRQHandler                         ;ADC0 threshold compare and error.
+        DCD     DMIC0_IRQHandler                              ;Digital microphone and DMIC subsystem
+        DCD     HWVAD0_IRQHandler                             ;Hardware Voice Activity Detector
+        DCD     USB0_NEEDCLK_IRQHandler                       ;USB Activity Wake-up Interrupt
+        DCD     USB0_IRQHandler                               ;USB device
+        DCD     RTC_IRQHandler                                ;RTC alarm and wake-up interrupts
+        DCD     Reserved46_IRQHandler                         ;Reserved interrupt
+        DCD     Reserved47_IRQHandler                         ;Reserved interrupt
+        DCD     PIN_INT4_IRQHandler                           ;Pin interrupt 4 or pattern match engine slice 4 int
+        DCD     PIN_INT5_IRQHandler                           ;Pin interrupt 5 or pattern match engine slice 5 int
+        DCD     PIN_INT6_IRQHandler                           ;Pin interrupt 6 or pattern match engine slice 6 int
+        DCD     PIN_INT7_IRQHandler                           ;Pin interrupt 7 or pattern match engine slice 7 int
+        DCD     CTIMER2_IRQHandler                            ;Standard counter/timer CTIMER2
+        DCD     CTIMER4_IRQHandler                            ;Standard counter/timer CTIMER4
+        DCD     RIT_IRQHandler                                ;Repetitive Interrupt Timer
+        DCD     SPIFI0_IRQHandler                             ;SPI flash interface
+        DCD     FLEXCOMM8_IRQHandler                          ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM9_IRQHandler                          ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+        DCD     SDIO_IRQHandler                               ;SD/MMC
+        DCD     CAN0_IRQ0_IRQHandler                          ;CAN0 interrupt0
+        DCD     CAN0_IRQ1_IRQHandler                          ;CAN0 interrupt1
+        DCD     CAN1_IRQ0_IRQHandler                          ;CAN1 interrupt0
+        DCD     CAN1_IRQ1_IRQHandler                          ;CAN1 interrupt1
+        DCD     USB1_IRQHandler                               ;USB1 interrupt
+        DCD     USB1_NEEDCLK_IRQHandler                       ;USB1 activity
+        DCD     ETHERNET_IRQHandler                           ;Ethernet
+        DCD     ETHERNET_PMT_IRQHandler                       ;Ethernet power management interrupt
+        DCD     ETHERNET_MACLP_IRQHandler                     ;Ethernet MAC interrupt
+        DCD     EEPROM_IRQHandler                             ;EEPROM interrupt
+        DCD     LCD_IRQHandler                                ;LCD interrupt
+        DCD     SHA_IRQHandler                                ;SHA interrupt
+        DCD     SMARTCARD0_IRQHandler                         ;Smart card 0 interrupt
+        DCD     SMARTCARD1_IRQHandler                         ;Smart card 1 interrupt
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        MOVS    r0,#56
+        LDR     r1, =0x40000220
+        STR     r0, [r1]           ;Enable SRAM clock used by Stack
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK WDT_BOD_IRQHandler
+        PUBWEAK WDT_BOD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+        LDR     R0, =WDT_BOD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT0_IRQHandler
+        PUBWEAK GINT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+        LDR     R0, =GINT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT1_IRQHandler
+        PUBWEAK GINT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+        LDR     R0, =GINT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT0_IRQHandler
+        PUBWEAK PIN_INT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+        LDR     R0, =PIN_INT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT1_IRQHandler
+        PUBWEAK PIN_INT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+        LDR     R0, =PIN_INT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT2_IRQHandler
+        PUBWEAK PIN_INT2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+        LDR     R0, =PIN_INT2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT3_IRQHandler
+        PUBWEAK PIN_INT3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+        LDR     R0, =PIN_INT3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK UTICK0_IRQHandler
+        PUBWEAK UTICK0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+        LDR     R0, =UTICK0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK MRT0_IRQHandler
+        PUBWEAK MRT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+        LDR     R0, =MRT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER0_IRQHandler
+        PUBWEAK CTIMER0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+        LDR     R0, =CTIMER0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER1_IRQHandler
+        PUBWEAK CTIMER1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+        LDR     R0, =CTIMER1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SCT0_IRQHandler
+        PUBWEAK SCT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+        LDR     R0, =SCT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER3_IRQHandler
+        PUBWEAK CTIMER3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+        LDR     R0, =CTIMER3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM0_IRQHandler
+        PUBWEAK FLEXCOMM0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+        LDR     R0, =FLEXCOMM0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM1_IRQHandler
+        PUBWEAK FLEXCOMM1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+        LDR     R0, =FLEXCOMM1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM2_IRQHandler
+        PUBWEAK FLEXCOMM2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+        LDR     R0, =FLEXCOMM2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM3_IRQHandler
+        PUBWEAK FLEXCOMM3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+        LDR     R0, =FLEXCOMM3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM4_IRQHandler
+        PUBWEAK FLEXCOMM4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+        LDR     R0, =FLEXCOMM4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM5_IRQHandler
+        PUBWEAK FLEXCOMM5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+        LDR     R0, =FLEXCOMM5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM6_IRQHandler
+        PUBWEAK FLEXCOMM6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+        LDR     R0, =FLEXCOMM6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM7_IRQHandler
+        PUBWEAK FLEXCOMM7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+        LDR     R0, =FLEXCOMM7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQA_IRQHandler
+        PUBWEAK ADC0_SEQA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+        LDR     R0, =ADC0_SEQA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQB_IRQHandler
+        PUBWEAK ADC0_SEQB_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+        LDR     R0, =ADC0_SEQB_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_THCMP_IRQHandler
+        PUBWEAK ADC0_THCMP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+        LDR     R0, =ADC0_THCMP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMIC0_IRQHandler
+        PUBWEAK DMIC0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+        LDR     R0, =DMIC0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK HWVAD0_IRQHandler
+        PUBWEAK HWVAD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+        LDR     R0, =HWVAD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_NEEDCLK_IRQHandler
+        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK USB0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+        LDR     R0, =USB0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+        LDR     R0, =RTC_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved46_IRQHandler
+        PUBWEAK Reserved46_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+        LDR     R0, =Reserved46_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved47_IRQHandler
+        PUBWEAK Reserved47_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+        LDR     R0, =Reserved47_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT4_IRQHandler
+        PUBWEAK PIN_INT4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+        LDR     R0, =PIN_INT4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT5_IRQHandler
+        PUBWEAK PIN_INT5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+        LDR     R0, =PIN_INT5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT6_IRQHandler
+        PUBWEAK PIN_INT6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+        LDR     R0, =PIN_INT6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT7_IRQHandler
+        PUBWEAK PIN_INT7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+        LDR     R0, =PIN_INT7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER2_IRQHandler
+        PUBWEAK CTIMER2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+        LDR     R0, =CTIMER2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER4_IRQHandler
+        PUBWEAK CTIMER4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+        LDR     R0, =CTIMER4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RIT_IRQHandler
+        PUBWEAK RIT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+        LDR     R0, =RIT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SPIFI0_IRQHandler
+        PUBWEAK SPIFI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+        LDR     R0, =SPIFI0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM8_IRQHandler
+        PUBWEAK FLEXCOMM8_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+        LDR     R0, =FLEXCOMM8_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM9_IRQHandler
+        PUBWEAK FLEXCOMM9_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+        LDR     R0, =FLEXCOMM9_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SDIO_IRQHandler
+        PUBWEAK SDIO_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+        LDR     R0, =SDIO_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ0_IRQHandler
+        PUBWEAK CAN0_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+        LDR     R0, =CAN0_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ1_IRQHandler
+        PUBWEAK CAN0_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+        LDR     R0, =CAN0_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ0_IRQHandler
+        PUBWEAK CAN1_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+        LDR     R0, =CAN1_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ1_IRQHandler
+        PUBWEAK CAN1_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+        LDR     R0, =CAN1_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_IRQHandler
+        PUBWEAK USB1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+        LDR     R0, =USB1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_NEEDCLK_IRQHandler
+        PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+        LDR     R0, =USB1_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_IRQHandler
+        PUBWEAK ETHERNET_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+        LDR     R0, =ETHERNET_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_PMT_IRQHandler
+        PUBWEAK ETHERNET_PMT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+        LDR     R0, =ETHERNET_PMT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_MACLP_IRQHandler
+        PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+        LDR     R0, =ETHERNET_MACLP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK EEPROM_IRQHandler
+        PUBWEAK EEPROM_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+        LDR     R0, =EEPROM_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LCD_IRQHandler
+        PUBWEAK LCD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+        LDR     R0, =LCD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SHA_IRQHandler
+        PUBWEAK SHA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+        LDR     R0, =SHA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD0_IRQHandler
+        PUBWEAK SMARTCARD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+        LDR     R0, =SMARTCARD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD1_IRQHandler
+        PUBWEAK SMARTCARD1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+        LDR     R0, =SMARTCARD1_DriverIRQHandler
+        BX      R0
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+        B .
+
+        END
@@ -0,0 +1,654 @@
+; -------------------------------------------------------------------------
+;  @file:    startup_LPC54628.s
+;  @purpose: CMSIS Cortex-M4 Core Device Startup File
+;            LPC54628
+;  @version: 2.0
+;  @date:    2024-10-29
+;  @build:   b250521
+; -------------------------------------------------------------------------
+;
+; Copyright 1997-2016 Freescale Semiconductor, Inc.
+; Copyright 2016-2025 NXP
+; SPDX-License-Identifier: BSD-3-Clause
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__iar_init$$done:              ; The vector table is not needed
+                      ; until after copy initialization is done
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     MemManage_Handler                             ;MPU Fault Handler
+        DCD     BusFault_Handler                              ;Bus Fault Handler
+        DCD     UsageFault_Handler                            ;Usage Fault Handler
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0xFFFFFFFF                                    ;ECRP
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     DebugMon_Handler                              ;Debug Monitor Handler
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     WDT_BOD_IRQHandler                            ;Windowed watchdog timer, Brownout detect
+        DCD     DMA0_IRQHandler                               ;DMA controller
+        DCD     GINT0_IRQHandler                              ;GPIO group 0
+        DCD     GINT1_IRQHandler                              ;GPIO group 1
+        DCD     PIN_INT0_IRQHandler                           ;Pin interrupt 0 or pattern match engine slice 0
+        DCD     PIN_INT1_IRQHandler                           ;Pin interrupt 1or pattern match engine slice 1
+        DCD     PIN_INT2_IRQHandler                           ;Pin interrupt 2 or pattern match engine slice 2
+        DCD     PIN_INT3_IRQHandler                           ;Pin interrupt 3 or pattern match engine slice 3
+        DCD     UTICK0_IRQHandler                             ;Micro-tick Timer
+        DCD     MRT0_IRQHandler                               ;Multi-rate timer
+        DCD     CTIMER0_IRQHandler                            ;Standard counter/timer CTIMER0
+        DCD     CTIMER1_IRQHandler                            ;Standard counter/timer CTIMER1
+        DCD     SCT0_IRQHandler                               ;SCTimer/PWM
+        DCD     CTIMER3_IRQHandler                            ;Standard counter/timer CTIMER3
+        DCD     FLEXCOMM0_IRQHandler                          ;Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM1_IRQHandler                          ;Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM2_IRQHandler                          ;Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM3_IRQHandler                          ;Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM4_IRQHandler                          ;Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM5_IRQHandler                          ;Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+        DCD     FLEXCOMM6_IRQHandler                          ;Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     FLEXCOMM7_IRQHandler                          ;Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     ADC0_SEQA_IRQHandler                          ;ADC0 sequence A completion.
+        DCD     ADC0_SEQB_IRQHandler                          ;ADC0 sequence B completion.
+        DCD     ADC0_THCMP_IRQHandler                         ;ADC0 threshold compare and error.
+        DCD     DMIC0_IRQHandler                              ;Digital microphone and DMIC subsystem
+        DCD     HWVAD0_IRQHandler                             ;Hardware Voice Activity Detector
+        DCD     USB0_NEEDCLK_IRQHandler                       ;USB Activity Wake-up Interrupt
+        DCD     USB0_IRQHandler                               ;USB device
+        DCD     RTC_IRQHandler                                ;RTC alarm and wake-up interrupts
+        DCD     Reserved46_IRQHandler                         ;Reserved interrupt
+        DCD     Reserved47_IRQHandler                         ;Reserved interrupt
+        DCD     PIN_INT4_IRQHandler                           ;Pin interrupt 4 or pattern match engine slice 4 int
+        DCD     PIN_INT5_IRQHandler                           ;Pin interrupt 5 or pattern match engine slice 5 int
+        DCD     PIN_INT6_IRQHandler                           ;Pin interrupt 6 or pattern match engine slice 6 int
+        DCD     PIN_INT7_IRQHandler                           ;Pin interrupt 7 or pattern match engine slice 7 int
+        DCD     CTIMER2_IRQHandler                            ;Standard counter/timer CTIMER2
+        DCD     CTIMER4_IRQHandler                            ;Standard counter/timer CTIMER4
+        DCD     RIT_IRQHandler                                ;Repetitive Interrupt Timer
+        DCD     SPIFI0_IRQHandler                             ;SPI flash interface
+        DCD     FLEXCOMM8_IRQHandler                          ;Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM9_IRQHandler                          ;Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+        DCD     SDIO_IRQHandler                               ;SD/MMC
+        DCD     CAN0_IRQ0_IRQHandler                          ;CAN0 interrupt0
+        DCD     CAN0_IRQ1_IRQHandler                          ;CAN0 interrupt1
+        DCD     CAN1_IRQ0_IRQHandler                          ;CAN1 interrupt0
+        DCD     CAN1_IRQ1_IRQHandler                          ;CAN1 interrupt1
+        DCD     USB1_IRQHandler                               ;USB1 interrupt
+        DCD     USB1_NEEDCLK_IRQHandler                       ;USB1 activity
+        DCD     ETHERNET_IRQHandler                           ;Ethernet
+        DCD     ETHERNET_PMT_IRQHandler                       ;Ethernet power management interrupt
+        DCD     ETHERNET_MACLP_IRQHandler                     ;Ethernet MAC interrupt
+        DCD     EEPROM_IRQHandler                             ;EEPROM interrupt
+        DCD     LCD_IRQHandler                                ;LCD interrupt
+        DCD     SHA_IRQHandler                                ;SHA interrupt
+        DCD     SMARTCARD0_IRQHandler                         ;Smart card 0 interrupt
+        DCD     SMARTCARD1_IRQHandler                         ;Smart card 1 interrupt
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        MOVS    r0,#56
+        LDR     r1, =0x40000220
+        STR     r0, [r1]           ;Enable SRAM clock used by Stack
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK WDT_BOD_IRQHandler
+        PUBWEAK WDT_BOD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+        LDR     R0, =WDT_BOD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT0_IRQHandler
+        PUBWEAK GINT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+        LDR     R0, =GINT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK GINT1_IRQHandler
+        PUBWEAK GINT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+        LDR     R0, =GINT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT0_IRQHandler
+        PUBWEAK PIN_INT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+        LDR     R0, =PIN_INT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT1_IRQHandler
+        PUBWEAK PIN_INT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+        LDR     R0, =PIN_INT1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT2_IRQHandler
+        PUBWEAK PIN_INT2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+        LDR     R0, =PIN_INT2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT3_IRQHandler
+        PUBWEAK PIN_INT3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+        LDR     R0, =PIN_INT3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK UTICK0_IRQHandler
+        PUBWEAK UTICK0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+        LDR     R0, =UTICK0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK MRT0_IRQHandler
+        PUBWEAK MRT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+        LDR     R0, =MRT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER0_IRQHandler
+        PUBWEAK CTIMER0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+        LDR     R0, =CTIMER0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER1_IRQHandler
+        PUBWEAK CTIMER1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+        LDR     R0, =CTIMER1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SCT0_IRQHandler
+        PUBWEAK SCT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+        LDR     R0, =SCT0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER3_IRQHandler
+        PUBWEAK CTIMER3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+        LDR     R0, =CTIMER3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM0_IRQHandler
+        PUBWEAK FLEXCOMM0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+        LDR     R0, =FLEXCOMM0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM1_IRQHandler
+        PUBWEAK FLEXCOMM1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+        LDR     R0, =FLEXCOMM1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM2_IRQHandler
+        PUBWEAK FLEXCOMM2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+        LDR     R0, =FLEXCOMM2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM3_IRQHandler
+        PUBWEAK FLEXCOMM3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+        LDR     R0, =FLEXCOMM3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM4_IRQHandler
+        PUBWEAK FLEXCOMM4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+        LDR     R0, =FLEXCOMM4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM5_IRQHandler
+        PUBWEAK FLEXCOMM5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+        LDR     R0, =FLEXCOMM5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM6_IRQHandler
+        PUBWEAK FLEXCOMM6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+        LDR     R0, =FLEXCOMM6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM7_IRQHandler
+        PUBWEAK FLEXCOMM7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+        LDR     R0, =FLEXCOMM7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQA_IRQHandler
+        PUBWEAK ADC0_SEQA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+        LDR     R0, =ADC0_SEQA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_SEQB_IRQHandler
+        PUBWEAK ADC0_SEQB_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+        LDR     R0, =ADC0_SEQB_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ADC0_THCMP_IRQHandler
+        PUBWEAK ADC0_THCMP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+        LDR     R0, =ADC0_THCMP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMIC0_IRQHandler
+        PUBWEAK DMIC0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+        LDR     R0, =DMIC0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK HWVAD0_IRQHandler
+        PUBWEAK HWVAD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+        LDR     R0, =HWVAD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_NEEDCLK_IRQHandler
+        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK USB0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+        LDR     R0, =USB0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+        LDR     R0, =RTC_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved46_IRQHandler
+        PUBWEAK Reserved46_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+        LDR     R0, =Reserved46_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved47_IRQHandler
+        PUBWEAK Reserved47_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+        LDR     R0, =Reserved47_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT4_IRQHandler
+        PUBWEAK PIN_INT4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+        LDR     R0, =PIN_INT4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT5_IRQHandler
+        PUBWEAK PIN_INT5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+        LDR     R0, =PIN_INT5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT6_IRQHandler
+        PUBWEAK PIN_INT6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+        LDR     R0, =PIN_INT6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK PIN_INT7_IRQHandler
+        PUBWEAK PIN_INT7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+        LDR     R0, =PIN_INT7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER2_IRQHandler
+        PUBWEAK CTIMER2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+        LDR     R0, =CTIMER2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CTIMER4_IRQHandler
+        PUBWEAK CTIMER4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+        LDR     R0, =CTIMER4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK RIT_IRQHandler
+        PUBWEAK RIT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+        LDR     R0, =RIT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SPIFI0_IRQHandler
+        PUBWEAK SPIFI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+        LDR     R0, =SPIFI0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM8_IRQHandler
+        PUBWEAK FLEXCOMM8_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+        LDR     R0, =FLEXCOMM8_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXCOMM9_IRQHandler
+        PUBWEAK FLEXCOMM9_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+        LDR     R0, =FLEXCOMM9_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SDIO_IRQHandler
+        PUBWEAK SDIO_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+        LDR     R0, =SDIO_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ0_IRQHandler
+        PUBWEAK CAN0_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+        LDR     R0, =CAN0_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN0_IRQ1_IRQHandler
+        PUBWEAK CAN0_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+        LDR     R0, =CAN0_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ0_IRQHandler
+        PUBWEAK CAN1_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+        LDR     R0, =CAN1_IRQ0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK CAN1_IRQ1_IRQHandler
+        PUBWEAK CAN1_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+        LDR     R0, =CAN1_IRQ1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_IRQHandler
+        PUBWEAK USB1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+        LDR     R0, =USB1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK USB1_NEEDCLK_IRQHandler
+        PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+        LDR     R0, =USB1_NEEDCLK_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_IRQHandler
+        PUBWEAK ETHERNET_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+        LDR     R0, =ETHERNET_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_PMT_IRQHandler
+        PUBWEAK ETHERNET_PMT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+        LDR     R0, =ETHERNET_PMT_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK ETHERNET_MACLP_IRQHandler
+        PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+        LDR     R0, =ETHERNET_MACLP_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK EEPROM_IRQHandler
+        PUBWEAK EEPROM_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+        LDR     R0, =EEPROM_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LCD_IRQHandler
+        PUBWEAK LCD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+        LDR     R0, =LCD_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SHA_IRQHandler
+        PUBWEAK SHA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+        LDR     R0, =SHA_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD0_IRQHandler
+        PUBWEAK SMARTCARD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+        LDR     R0, =SMARTCARD0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK SMARTCARD1_IRQHandler
+        PUBWEAK SMARTCARD1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+        LDR     R0, =SMARTCARD1_DriverIRQHandler
+        BX      R0
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+        B .
+
+        END