shell/LonganTFReader
1
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
shell committed 2026-10-11 21:48:59 +08:00
commit b44ce7bd77
2716 files changed
+559005
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

third_party/tinyusb/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
Vendored
+153
View File
@@ -0,0 +1,153 @@
/*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
// skip if included from IAR assembler
#ifndef __IASMARM__
#include "fsl_device_registers.h"
#endif
/* Cortex M23/M33 port configuration. */
#define configENABLE_MPU 0
#if defined(__ARM_FP) && __ARM_FP >= 4
#define configENABLE_FPU 1
#else
#define configENABLE_FPU 0
#endif
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE (1024)
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configCPU_CLOCK_HZ SystemCoreClock
#define configTICK_RATE_HZ ( 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( 128 )
#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
#define configMAX_TASK_NAME_LEN 16
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configQUEUE_REGISTRY_SIZE 4
#define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 0
#define configUSE_NEWLIB_REENTRANT 0
#define configENABLE_BACKWARD_COMPATIBILITY 1
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 0
/* Hook function related definitions. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configCHECK_HANDLER_INSTALLATION 0
/* Run time and task stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS 0
#define configRECORD_STACK_HIGH_ADDRESS 1
#define configUSE_TRACE_FACILITY 1 // legacy trace
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES 2
/* Software timer related definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
#define configTIMER_QUEUE_LENGTH 32
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
/* Optional functions - most linkers will remove unused functions anyway. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
#define INCLUDE_xResumeFromISR 0
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
#define INCLUDE_pcTaskGetTaskName 0
#define INCLUDE_eTaskGetState 0
#define INCLUDE_xEventGroupSetBitFromISR 0
#define INCLUDE_xTimerPendFunctionCall 0
/* FreeRTOS hooks to NVIC vectors */
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#define vPortSVCHandler SVC_Handler
//--------------------------------------------------------------------+
// Interrupt nesting behavior configuration.
//--------------------------------------------------------------------+
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
#define configPRIO_BITS 3
/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#endif
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
Vendored
+25
View File
@@ -0,0 +1,25 @@
set(MCU_VARIANT MCXA153)
set(MCU_FAMILY MCXA)
set(MCU_CORE MCXA153)
set(JLINK_DEVICE MCXA153_M33)
set(PYOCD_TARGET MCXA153)
set(NXPLINK_DEVICE MCXA153:MCXA153)
set(PORT 0)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_MCXA153VLH
BOARD_TUD_RHPORT=0
BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
CFG_EXAMPLE_VIDEO_READONLY
)
target_sources(${TARGET} PRIVATE
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
)
target_include_directories(${TARGET} PUBLIC
${SDK_DIR}/${MCU_FAMILY}/periph
)
endfunction()
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/board.h
Vendored
+69
View File
@@ -0,0 +1,69 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: Freedom MCXA153
url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_GPIO GPIO3
#define LED_CLK kCLOCK_GateGPIO3
#define LED_PIN 12 //red
#define LED_STATE_ON 0
// ISP button
#define BUTTON_GPIO GPIO3
#define BUTTON_CLK kCLOCK_GateGPIO3
#define BUTTON_PIN 29 //sw2
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART0
static inline void board_uart_init_clock(void) {
/* attach 12 MHz clock to LPUART0 (debug console) */
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
}
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
Vendored
+23
View File
@@ -0,0 +1,23 @@
MCU_VARIANT = MCXA153
MCU_FAMILY = MCXA
MCU_CORE = MCXA153
PORT = 0
CPU_CORE = cortex-m33-nodsp-nofp
CFLAGS += \
-DCPU_MCXA153VLH \
-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
-DCFG_EXAMPLE_VIDEO_READONLY
SRC_C += \
${BOARD_PATH}/clock_config.c \
${BOARD_PATH}/pin_mux.c
INC += \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph
JLINK_DEVICE = MCXA153
PYOCD_TARGET = MCXA153
# flash using pyocd
flash: flash-jlink
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
Vendored
+559
View File
@@ -0,0 +1,559 @@
/*
* Copyright 2025 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v18.0
processor: MCXA153
package_id: MCXA153VLH
mcu_data: ksdk2_0
processor_version: 25.09.10
board: FRDM-MCXA153
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_clock.h"
#include "clock_config.h"
#include "fsl_spc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockFRO96M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CPU_clock.outFreq, value: 12 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 12 MHz}
- {id: Slow_clock.outFreq, value: 3 MHz}
- {id: System_clock.outFreq, value: 12 MHz}
- {id: TRACE_clock.outFreq, value: 12 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
- {id: WWDT0_clock.outFreq, value: 1 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
/*!< Set up system dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO24M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 24 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 6 MHz}
- {id: System_clock.outFreq, value: 24 MHz}
- {id: TRACE_clock.outFreq, value: 24 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
- {id: WWDT0_clock.outFreq, value: 1 MHz}
settings:
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '2'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO24M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO24M configuration
******************************************************************************/
void BOARD_BootClockFRO24M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
/*!< Set up system dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO48M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 12 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
- {id: TRACE_clock.outFreq, value: 48 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
- {id: WWDT0_clock.outFreq, value: 1 MHz}
settings:
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO48M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO48M configuration
******************************************************************************/
void BOARD_BootClockFRO48M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
/*!< Set up system dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO64M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 64 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
- {id: FRO_HF_clock.outFreq, value: 64 MHz}
- {id: MAIN_clock.outFreq, value: 64 MHz}
- {id: Slow_clock.outFreq, value: 16 MHz}
- {id: System_clock.outFreq, value: 64 MHz}
- {id: TRACE_clock.outFreq, value: 64 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
- {id: WWDT0_clock.outFreq, value: 1 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
sources:
- {id: SCG.FIRC.outFreq, value: 64 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO64M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO64M configuration
******************************************************************************/
void BOARD_BootClockFRO64M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
/*!< Set up system dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO96M
called_from_default_init: true
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 96 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
- {id: FRO_HF_clock.outFreq, value: 96 MHz}
- {id: MAIN_clock.outFreq, value: 96 MHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 96 MHz}
- {id: TRACE_clock.outFreq, value: 96 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
- {id: WWDT0_clock.outFreq, value: 1 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
sources:
- {id: SCG.FIRC.outFreq, value: 96 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO96M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO96M configuration
******************************************************************************/
void BOARD_BootClockFRO96M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
/*!< Set up system dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
}
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h
Vendored
+385
View File
@@ -0,0 +1,385 @@
/*
* Copyright 2025 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFRO12M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFRO12M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO12M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
#define BOARD_BOOTCLOCKFRO12M_CLK_48M_CLOCK 0UL /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO12M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO12M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO12M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO12M_CPU_CLOCK 12000000UL /* Clock consumers of CPU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFRO12M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO12M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO12M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_FRO_HF_DIV_CLOCK 0UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_FRO_HF_CLOCK 0UL /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO12M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO12M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO12M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
#define BOARD_BOOTCLOCKFRO12M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
#define BOARD_BOOTCLOCKFRO12M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
#define BOARD_BOOTCLOCKFRO12M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
#define BOARD_BOOTCLOCKFRO12M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
#define BOARD_BOOTCLOCKFRO12M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
#define BOARD_BOOTCLOCKFRO12M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
#define BOARD_BOOTCLOCKFRO12M_MAIN_CLOCK 12000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
#define BOARD_BOOTCLOCKFRO12M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFRO12M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_SLOW_CLOCK 3000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 12000000UL /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFRO12M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO12M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO24M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFRO24M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFRO24M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO24M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
#define BOARD_BOOTCLOCKFRO24M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
#define BOARD_BOOTCLOCKFRO24M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO24M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO24M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO24M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO24M_CPU_CLOCK 24000000UL /* Clock consumers of CPU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFRO24M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFRO24M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFRO24M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO24M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO24M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_FRO_HF_DIV_CLOCK 48000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_FRO_HF_CLOCK 48000000UL /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO24M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO24M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO24M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
#define BOARD_BOOTCLOCKFRO24M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
#define BOARD_BOOTCLOCKFRO24M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
#define BOARD_BOOTCLOCKFRO24M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
#define BOARD_BOOTCLOCKFRO24M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
#define BOARD_BOOTCLOCKFRO24M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
#define BOARD_BOOTCLOCKFRO24M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
#define BOARD_BOOTCLOCKFRO24M_MAIN_CLOCK 48000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
#define BOARD_BOOTCLOCKFRO24M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFRO24M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_SLOW_CLOCK 6000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO24M_SYSTEM_CLOCK 24000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
#define BOARD_BOOTCLOCKFRO24M_TRACE_CLOCK 24000000UL /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFRO24M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
#define BOARD_BOOTCLOCKFRO24M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFRO24M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO24M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
/*******************************************************************************
* API for BOARD_BootClockFRO24M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO24M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO48M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFRO48M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFRO48M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO48M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
#define BOARD_BOOTCLOCKFRO48M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
#define BOARD_BOOTCLOCKFRO48M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO48M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO48M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO48M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO48M_CPU_CLOCK 48000000UL /* Clock consumers of CPU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFRO48M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFRO48M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFRO48M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO48M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO48M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_FRO_HF_DIV_CLOCK 48000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_FRO_HF_CLOCK 48000000UL /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO48M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO48M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO48M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
#define BOARD_BOOTCLOCKFRO48M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
#define BOARD_BOOTCLOCKFRO48M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
#define BOARD_BOOTCLOCKFRO48M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
#define BOARD_BOOTCLOCKFRO48M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
#define BOARD_BOOTCLOCKFRO48M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
#define BOARD_BOOTCLOCKFRO48M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
#define BOARD_BOOTCLOCKFRO48M_MAIN_CLOCK 48000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
#define BOARD_BOOTCLOCKFRO48M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFRO48M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_SLOW_CLOCK 12000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO48M_SYSTEM_CLOCK 48000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
#define BOARD_BOOTCLOCKFRO48M_TRACE_CLOCK 48000000UL /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFRO48M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
#define BOARD_BOOTCLOCKFRO48M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFRO48M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO48M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
/*******************************************************************************
* API for BOARD_BootClockFRO48M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO48M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO64M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFRO64M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFRO64M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO64M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
#define BOARD_BOOTCLOCKFRO64M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
#define BOARD_BOOTCLOCKFRO64M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO64M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO64M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO64M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO64M_CPU_CLOCK 64000000UL /* Clock consumers of CPU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFRO64M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFRO64M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFRO64M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO64M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO64M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_FRO_HF_DIV_CLOCK 64000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_FRO_HF_CLOCK 64000000UL /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO64M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO64M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO64M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
#define BOARD_BOOTCLOCKFRO64M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
#define BOARD_BOOTCLOCKFRO64M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
#define BOARD_BOOTCLOCKFRO64M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
#define BOARD_BOOTCLOCKFRO64M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
#define BOARD_BOOTCLOCKFRO64M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
#define BOARD_BOOTCLOCKFRO64M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
#define BOARD_BOOTCLOCKFRO64M_MAIN_CLOCK 64000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
#define BOARD_BOOTCLOCKFRO64M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFRO64M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_SLOW_CLOCK 16000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO64M_SYSTEM_CLOCK 64000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
#define BOARD_BOOTCLOCKFRO64M_TRACE_CLOCK 64000000UL /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFRO64M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
#define BOARD_BOOTCLOCKFRO64M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFRO64M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO64M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
/*******************************************************************************
* API for BOARD_BootClockFRO64M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO64M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO96M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKFRO96M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
#define BOARD_BOOTCLOCKFRO96M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO96M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */
#define BOARD_BOOTCLOCKFRO96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */
#define BOARD_BOOTCLOCKFRO96M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO96M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
#define BOARD_BOOTCLOCKFRO96M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO96M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
#define BOARD_BOOTCLOCKFRO96M_CPU_CLOCK 96000000UL /* Clock consumers of CPU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
#define BOARD_BOOTCLOCKFRO96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
#define BOARD_BOOTCLOCKFRO96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
#define BOARD_BOOTCLOCKFRO96M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO96M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
#define BOARD_BOOTCLOCKFRO96M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_FRO_HF_DIV_CLOCK 96000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_FRO_HF_CLOCK 96000000UL /* Clock consumers of FRO_HF_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO96M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO96M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */
#define BOARD_BOOTCLOCKFRO96M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */
#define BOARD_BOOTCLOCKFRO96M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */
#define BOARD_BOOTCLOCKFRO96M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */
#define BOARD_BOOTCLOCKFRO96M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */
#define BOARD_BOOTCLOCKFRO96M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */
#define BOARD_BOOTCLOCKFRO96M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */
#define BOARD_BOOTCLOCKFRO96M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */
#define BOARD_BOOTCLOCKFRO96M_MAIN_CLOCK 96000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */
#define BOARD_BOOTCLOCKFRO96M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
#define BOARD_BOOTCLOCKFRO96M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_SLOW_CLOCK 24000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */
#define BOARD_BOOTCLOCKFRO96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */
#define BOARD_BOOTCLOCKFRO96M_TRACE_CLOCK 96000000UL /* Clock consumers of TRACE_clock output : SWD */
#define BOARD_BOOTCLOCKFRO96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */
#define BOARD_BOOTCLOCKFRO96M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */
#define BOARD_BOOTCLOCKFRO96M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */
#define BOARD_BOOTCLOCKFRO96M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */
/*******************************************************************************
* API for BOARD_BootClockFRO96M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO96M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex
Vendored
+573
View File
@@ -0,0 +1,573 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="FRDM-MCXA153" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_19 http://mcuxpresso.nxp.com/XSD/mex_configuration_19.xsd" uuid="39087bef-8f98-40a9-aaf4-e556fb7a1ce1" version="19" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_19" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MCXA153</processor>
<package>MCXA153VLH</package>
<board>FRDM-MCXA153</board>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="cm33_core0">
<core name="Cortex-M33" id="cm33_core0" description="M33 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<custom_copyright>
<text>/*
* Copyright 2025 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
</text>
<enabled>true</enabled>
</custom_copyright>
<update_include_paths>true</update_include_paths>
<enable_parallel_routing>true</enable_parallel_routing>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>25.09.10</processor_version>
<external_user_signals>
<properties/>
</external_user_signals>
</pins_profile>
<functions_list>
<function name="BOARD_InitDEBUG_UARTPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>cm33_core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART0" description="Peripheral LPUART0 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART0" signal="RX" pin_num="51" pin_signal="P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="high"/>
<pin_feature name="pull_select" value="down"/>
<pin_feature name="pull_enable" value="disable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
<pin peripheral="LPUART0" signal="TX" pin_num="52" pin_signal="P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="up"/>
<pin_feature name="pull_enable" value="enable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
</pins>
</function>
<function name="BOARD_InitSWD_DEBUGPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>false</callFromInitBoot>
<coreID>cm33_core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="SWD" description="Peripheral SWD signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSWD_DEBUGPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitSWD_DEBUGPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="SWD" signal="SWCLK" pin_num="50" pin_signal="P0_1/TCLK/SWCLK/LPUART0_CTS_B/LPSPI0_SDI/CT_INP1">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="down"/>
<pin_feature name="pull_enable" value="enable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
<pin peripheral="SWD" signal="SWDIO" pin_num="49" pin_signal="P0_0/TMS/SWDIO/LPUART0_RTS_B/LPSPI0_PCS0/CT_INP0">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="high"/>
<pin_feature name="pull_select" value="up"/>
<pin_feature name="pull_enable" value="enable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
<pin peripheral="SWD" signal="SWO" pin_num="51" pin_signal="P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="high"/>
<pin_feature name="pull_select" value="down"/>
<pin_feature name="pull_enable" value="disable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
</pins>
</function>
<function name="BOARD_InitLEDsPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>cm33_core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.gpio" description="Pins initialization requires the GPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDsPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO3" signal="GPIO, 13" pin_num="37" pin_signal="P3_13/LPUART2_CTS_B/CT1_MAT3/PWM0_X1">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="gpio_init_state" value="true"/>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="up"/>
<pin_feature name="pull_enable" value="disable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
<pin peripheral="GPIO3" signal="GPIO, 12" pin_num="38" pin_signal="P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="gpio_init_state" value="true"/>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="up"/>
<pin_feature name="pull_enable" value="disable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
<pin peripheral="GPIO3" signal="GPIO, 0" pin_num="46" pin_signal="P3_0/WUU0_IN22/TRIG_IN0/CT_INP16/PWM0_A0">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="gpio_init_state" value="true"/>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="up"/>
<pin_feature name="pull_enable" value="disable"/>
<pin_feature name="passive_filter" value="disable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
</pins>
</function>
<function name="BOARD_InitBUTTONsPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>cm33_core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.port" description="Pins initialization requires the PORT Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONsPins">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO1" signal="GPIO, 7" pin_num="1" pin_signal="P1_7/WUU0_IN9/TRIG_OUT2/LPUART2_CTS_B/CT_INP7/ADC0_A23">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="down"/>
<pin_feature name="pull_enable" value="disable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="GPIO, 29" pin_num="8" pin_signal="P1_29/RESET_B/SPC_LPREQ">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="enable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="up"/>
<pin_feature name="pull_enable" value="enable"/>
<pin_feature name="passive_filter" value="enable"/>
<pin_feature name="pull_value" value="low"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
<pin peripheral="GPIO3" signal="GPIO, 29" pin_num="32" pin_signal="P3_29/WUU0_IN27/ISPMODE_N/CT_INP3/ADC0_A14">
<pin_features>
<pin_feature name="slew_rate" value="fast"/>
<pin_feature name="open_drain" value="disable"/>
<pin_feature name="drive_strength" value="low"/>
<pin_feature name="pull_select" value="up"/>
<pin_feature name="pull_enable" value="enable"/>
<pin_feature name="input_buffer" value="enable"/>
<pin_feature name="invert_input" value="normal"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="18.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>25.09.10</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockFRO12M" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO12M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources/>
<clock_outputs>
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CPU_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="MAIN_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="Slow_clock.outFreq" value="3 MHz" locked="false" accuracy=""/>
<clock_output id="System_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="SCGMode" value="SIRC" locked="false"/>
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
<setting id="SCG.SCSSEL.sel" value="SCG.SIRC" locked="false"/>
<setting id="SCG_FIRCCSR_FIRCEN_CFG" value="Disabled" locked="false"/>
</clock_settings>
<called_from_default_init>false</called_from_default_init>
</clock_configuration>
<clock_configuration name="BOARD_BootClockFRO24M" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO24M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO24M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO24M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources/>
<clock_outputs>
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="CPU_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_DIV_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="MAIN_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="Slow_clock.outFreq" value="6 MHz" locked="false" accuracy=""/>
<clock_output id="System_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
<setting id="SYSCON.AHBCLKDIV.scale" value="2" locked="false"/>
</clock_settings>
<called_from_default_init>false</called_from_default_init>
</clock_configuration>
<clock_configuration name="BOARD_BootClockFRO48M" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO48M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO48M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO48M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources/>
<clock_outputs>
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="CPU_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_DIV_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="MAIN_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="Slow_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="System_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
</clock_settings>
<called_from_default_init>false</called_from_default_init>
</clock_configuration>
<clock_configuration name="BOARD_BootClockFRO64M" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO64M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO64M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO64M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="SCG.FIRC.outFreq" value="64 MHz" locked="false" enabled="false"/>
</clock_sources>
<clock_outputs>
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="CPU_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_DIV_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
<clock_output id="MAIN_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
<clock_output id="Slow_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
<clock_output id="System_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_clock.outFreq" value="64 MHz" locked="false" accuracy=""/>
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="VDD_CORE" value="voltage_1v1" locked="false"/>
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.FROHFDIV.scale" value="1" locked="true"/>
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
<setting id="SYSCON.AHBCLKDIV.scale" value="1" locked="true"/>
</clock_settings>
<called_from_default_init>false</called_from_default_init>
</clock_configuration>
<clock_configuration name="BOARD_BootClockFRO96M" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO96M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO96M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.mcx_spc" description="Clocks initialization requires the MCX_SPC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockFRO96M">
<feature name="enabled" evaluation="equal" configuration="cm33_core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="SCG.FIRC.outFreq" value="96 MHz" locked="false" enabled="false"/>
</clock_sources>
<clock_outputs>
<clock_output id="CLK_1M_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_48M_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
<clock_output id="CPU_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_12M_clock.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_DIV_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
<clock_output id="FRO_HF_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
<clock_output id="MAIN_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
<clock_output id="Slow_clock.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="System_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_clock.outFreq" value="96 MHz" locked="false" accuracy=""/>
<clock_output id="UTICK_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="WWDT0_clock.outFreq" value="1 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="VDD_CORE" value="voltage_1v1" locked="false"/>
<setting id="MRCC.FREQMEREFCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.FREQMETARGETCLKSEL.sel" value="MRCC.aoi0_out0" locked="false"/>
<setting id="MRCC.OSTIMERCLKSEL.sel" value="VBAT.CLK16K_1" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>N/A</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcdx>
<periphs name="Peripherals" version="15.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/peripherals.c" update_enabled="true"/>
<file path="board/peripherals.h" update_enabled="true"/>
</generated_project_files>
<peripherals_profile>
<processor_version>25.09.10</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="e7964cfd-63b7-4756-a1af-71a53c49bda7" called_from_default_init="true" id_prefix="" core="cm33_core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="NVIC" uuid="6948572f-4bff-423f-8e78-3f0608580bb3" type="nvic" type_id="nvic" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="3700167a-8497-4b9d-ad19-c395e5e33267" type_id="system">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
<setting name="global_init" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="faf79cc1-e0a0-4bf8-a803-42cf14e2a60a" type_id="msg">
<config_set_global name="global_messages"/>
</component>
<component name="generic_can" uuid="f1cb80d2-97a1-4bdd-ab65-0d3d8493019c" type_id="generic_can">
<config_set_global name="global_can"/>
</component>
<component name="uart_cmsis_common" uuid="a17f12aa-b188-417b-a499-c22892686ae2" type_id="uart_cmsis_common">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_uart" uuid="96c6481f-affb-44c4-9d6f-ebc972fcae38" type_id="generic_uart">
<config_set_global name="global_uart"/>
</component>
<component name="generic_enet" uuid="44df8b34-f20e-449a-8d2d-2cba12faf3f7" type_id="generic_enet">
<config_set_global name="global_enet"/>
</component>
<component name="gpio_adapter_common" uuid="2fe36bae-ef17-4655-9cf5-91cac6de7288" type_id="gpio_adapter_common">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
</components>
</periphs>
<tee name="TEE" version="10.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>N/A</processor_version>
</tee_profile>
</tee>
</tools>
</configuration>
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
Vendored
+492
View File
@@ -0,0 +1,492 @@
/*
* Copyright 2025 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v17.0
processor: MCXA153
package_id: MCXA153VLH
mcu_data: ksdk2_0
processor_version: 25.09.10
board: FRDM-MCXA153
external_user_signals: {}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitDEBUG_UARTPins();
BOARD_InitLEDsPins();
BOARD_InitBUTTONsPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
drive_strength: high, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void)
{
/* Write to PORT0: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* LPUART0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
/* PORT0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
.pullSelect = kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is disabled */
.passiveFilterEnable = kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
.openDrainEnable = kPORT_OpenDrainDisable,
/* High drive strength is configured */
.driveStrength = kPORT_HighDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_RXD */
.mux = kPORT_MuxAlt2,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT0_2 (pin 51) is configured as LPUART0_RXD */
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up resistor is enabled */
.pullSelect = kPORT_PullUp,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is disabled */
.passiveFilterEnable = kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
.openDrainEnable = kPORT_OpenDrainDisable,
/* Low drive strength is configured */
.driveStrength = kPORT_LowDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_TXD */
.mux = kPORT_MuxAlt2,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT0_3 (pin 52) is configured as LPUART0_TXD */
PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSWD_DEBUGPins:
- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '50', peripheral: SWD, signal: SWCLK, pin_signal: P0_1/TCLK/SWCLK/LPUART0_CTS_B/LPSPI0_SDI/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low,
pull_select: down, pull_enable: enable, input_buffer: enable, invert_input: normal}
- {pin_num: '49', peripheral: SWD, signal: SWDIO, pin_signal: P0_0/TMS/SWDIO/LPUART0_RTS_B/LPSPI0_PCS0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high,
pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
- {pin_num: '51', peripheral: SWD, signal: SWO, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
drive_strength: high, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitSWD_DEBUGPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSWD_DEBUGPins(void)
{
/* Write to PORT0: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* PORT0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
/* LPUART0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
const port_pin_config_t DEBUG_SWD_SWDIO = {/* Internal pull-up resistor is enabled */
.pullSelect = kPORT_PullUp,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is disabled */
.passiveFilterEnable = kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
.openDrainEnable = kPORT_OpenDrainDisable,
/* High drive strength is configured */
.driveStrength = kPORT_HighDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as SWDIO */
.mux = kPORT_MuxAlt1,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT0_0 (pin 49) is configured as SWDIO */
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, &DEBUG_SWD_SWDIO);
const port_pin_config_t DEBUG_SWD_SWDCLK = {/* Internal pull-down resistor is enabled */
.pullSelect = kPORT_PullDown,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is disabled */
.passiveFilterEnable = kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
.openDrainEnable = kPORT_OpenDrainDisable,
/* Low drive strength is configured */
.driveStrength = kPORT_LowDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as SWCLK */
.mux = kPORT_MuxAlt1,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT0_1 (pin 50) is configured as SWCLK */
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, &DEBUG_SWD_SWDCLK);
const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
.pullSelect = kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is disabled */
.passiveFilterEnable = kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
.openDrainEnable = kPORT_OpenDrainDisable,
/* High drive strength is configured */
.driveStrength = kPORT_HighDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as SWO */
.mux = kPORT_MuxAlt1,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT0_2 (pin 51) is configured as SWO */
PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitLEDsPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '37', peripheral: GPIO3, signal: 'GPIO, 13', pin_signal: P3_13/LPUART2_CTS_B/CT1_MAT3/PWM0_X1, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, input_buffer: enable, invert_input: normal}
- {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, input_buffer: enable, invert_input: normal}
- {pin_num: '46', peripheral: GPIO3, signal: 'GPIO, 0', pin_signal: P3_0/WUU0_IN22/TRIG_IN0/CT_INP16/PWM0_A0, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitLEDsPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitLEDsPins(void)
{
/* Write to GPIO3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GateGPIO3);
/* Write to PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT3);
/* GPIO3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
gpio_pin_config_t LED_BLUE_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 1U
};
/* Initialize GPIO functionality on pin PIO3_0 (pin 46) */
GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config);
gpio_pin_config_t LED_RED_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 1U
};
/* Initialize GPIO functionality on pin PIO3_12 (pin 38) */
GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config);
gpio_pin_config_t LED_GREEN_config = {
.pinDirection = kGPIO_DigitalOutput,
.outputLogic = 1U
};
/* Initialize GPIO functionality on pin PIO3_13 (pin 37) */
GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config);
/* PORT3_0 (pin 46) is configured as P3_0 */
PORT_SetPinMux(BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, kPORT_MuxAlt0);
PORT3->PCR[0] =
((PORT3->PCR[0] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK)))
/* Pull Select: Enables internal pullup resistor. */
| PORT_PCR_PS(PCR_PS_ps1)
/* Pull Enable: Disables. */
| PORT_PCR_PE(PCR_PE_pe0)
/* Slew Rate Enable: Fast. */
| PORT_PCR_SRE(PCR_SRE_sre0)
/* Passive Filter Enable: Disables. */
| PORT_PCR_PFE(PCR_PFE_pfe0)
/* Open Drain Enable: Disables. */
| PORT_PCR_ODE(PCR_ODE_ode0)
/* Drive Strength Enable: Low. */
| PORT_PCR_DSE(PCR_DSE_dse0)
/* Input Buffer Enable: Enables. */
| PORT_PCR_IBE(PCR_IBE_ibe1)
/* Invert Input: Does not invert. */
| PORT_PCR_INV(PCR_INV_inv0));
/* PORT3_12 (pin 38) is configured as P3_12 */
PORT_SetPinMux(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, kPORT_MuxAlt0);
PORT3->PCR[12] =
((PORT3->PCR[12] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK)))
/* Pull Select: Enables internal pullup resistor. */
| PORT_PCR_PS(PCR_PS_ps1)
/* Pull Enable: Disables. */
| PORT_PCR_PE(PCR_PE_pe0)
/* Slew Rate Enable: Fast. */
| PORT_PCR_SRE(PCR_SRE_sre0)
/* Open Drain Enable: Disables. */
| PORT_PCR_ODE(PCR_ODE_ode0)
/* Drive Strength Enable: Low. */
| PORT_PCR_DSE(PCR_DSE_dse0)
/* Input Buffer Enable: Enables. */
| PORT_PCR_IBE(PCR_IBE_ibe1)
/* Invert Input: Does not invert. */
| PORT_PCR_INV(PCR_INV_inv0));
/* PORT3_13 (pin 37) is configured as P3_13 */
PORT_SetPinMux(BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, kPORT_MuxAlt0);
PORT3->PCR[13] =
((PORT3->PCR[13] &
/* Mask bits to zero which are setting */
(~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK)))
/* Pull Select: Enables internal pullup resistor. */
| PORT_PCR_PS(PCR_PS_ps1)
/* Pull Enable: Disables. */
| PORT_PCR_PE(PCR_PE_pe0)
/* Slew Rate Enable: Fast. */
| PORT_PCR_SRE(PCR_SRE_sre0)
/* Open Drain Enable: Disables. */
| PORT_PCR_ODE(PCR_ODE_ode0)
/* Drive Strength Enable: Low. */
| PORT_PCR_DSE(PCR_DSE_dse0)
/* Input Buffer Enable: Enables. */
| PORT_PCR_IBE(PCR_IBE_ibe1)
/* Invert Input: Does not invert. */
| PORT_PCR_INV(PCR_INV_inv0));
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitBUTTONsPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '1', peripheral: GPIO1, signal: 'GPIO, 7', pin_signal: P1_7/WUU0_IN9/TRIG_OUT2/LPUART2_CTS_B/CT_INP7/ADC0_A23, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- {pin_num: '8', peripheral: GPIO1, signal: 'GPIO, 29', pin_signal: P1_29/RESET_B/SPC_LPREQ, slew_rate: fast, open_drain: enable, drive_strength: low, pull_select: up,
pull_enable: enable, passive_filter: enable, pull_value: low, input_buffer: enable, invert_input: normal}
- {pin_num: '32', peripheral: GPIO3, signal: 'GPIO, 29', pin_signal: P3_29/WUU0_IN27/ISPMODE_N/CT_INP3/ADC0_A14, slew_rate: fast, open_drain: disable, drive_strength: low,
pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBUTTONsPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitBUTTONsPins(void)
{
/* Write to PORT1: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT1);
/* Write to PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT3);
/* GPIO1 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
/* PORT1 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
/* GPIO3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
const port_pin_config_t SW1 = {/* Internal pull-up resistor is enabled */
.pullSelect = kPORT_PullUp,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is enabled */
.passiveFilterEnable = kPORT_PassiveFilterEnable,
/* Open drain output is enabled */
.openDrainEnable = kPORT_OpenDrainEnable,
/* Low drive strength is configured */
.driveStrength = kPORT_LowDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as P1_29 */
.mux = kPORT_MuxAlt0,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT1_29 (pin 8) is configured as P1_29 */
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW1_PORT, BOARD_INITBUTTONSPINS_SW1_PIN, &SW1);
const port_pin_config_t SW3 = {/* Internal pull-up/down resistor is disabled */
.pullSelect = kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is disabled */
.passiveFilterEnable = kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
.openDrainEnable = kPORT_OpenDrainDisable,
/* Low drive strength is configured */
.driveStrength = kPORT_LowDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as P1_7 */
.mux = kPORT_MuxAlt0,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT1_7 (pin 1) is configured as P1_7 */
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3);
const port_pin_config_t ISP = {/* Internal pull-up resistor is enabled */
.pullSelect = kPORT_PullUp,
/* Low internal pull resistor value is selected. */
.pullValueSelect = kPORT_LowPullResistor,
/* Fast slew rate is configured */
.slewRate = kPORT_FastSlewRate,
/* Passive input filter is disabled */
.passiveFilterEnable = kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
.openDrainEnable = kPORT_OpenDrainDisable,
/* Low drive strength is configured */
.driveStrength = kPORT_LowDriveStrength,
/* Normal drive strength is configured */
.driveStrength1 = kPORT_NormalDriveStrength,
/* Pin is configured as P3_29 */
.mux = kPORT_MuxAlt0,
/* Digital input enabled */
.inputBuffer = kPORT_InputBufferEnable,
/* Digital input is not inverted */
.invertInput = kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
.lockRegister = kPORT_UnlockRegister};
/* PORT3_29 (pin 32) is configured as P3_29 */
PORT_SetPinConfig(BOARD_INITBUTTONSPINS_ISP_PORT, BOARD_INITBUTTONSPINS_ISP_PIN, &ISP);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
Vendored
+211
View File
@@ -0,0 +1,211 @@
/*
* Copyright 2025 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*! @name PORT0_2 (number 51), P0_2/SWO/J25[3]/J18[6]
@{ */
/* Symbols to be used with PORT driver */
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT PORT0 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 2U /*!<@brief PORT pin number */
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PORT0_3 (number 52), P0_3/J25[1]/J18[8]
@{ */
/* Symbols to be used with PORT driver */
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT PORT0 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 3U /*!<@brief PORT pin number */
#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 3U) /*!<@brief PORT pin mask */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
/*! @name PORT0_1 (number 50), P0_1/SWCLK/JP10[2]/J18[4]
@{ */
/* Symbols to be used with PORT driver */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT PORT0 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 1U /*!<@brief PORT pin number */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PORT0_0 (number 49), P0_0/SWDIO/J18[2]
@{ */
/* Symbols to be used with PORT driver */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT PORT0 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 0U /*!<@brief PORT pin number */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PORT0_2 (number 51), P0_2/SWO/J25[3]/J18[6]
@{ */
/* Symbols to be used with PORT driver */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PORT PORT0 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN 2U /*!<@brief PORT pin number */
#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitSWD_DEBUGPins(void);
#define PCR_DSE_dse0 0x00u /*!<@brief Drive Strength Enable: Low */
#define PCR_IBE_ibe1 0x01u /*!<@brief Input Buffer Enable: Enables */
#define PCR_INV_inv0 0x00u /*!<@brief Invert Input: Does not invert */
#define PCR_ODE_ode0 0x00u /*!<@brief Open Drain Enable: Disables */
#define PCR_PE_pe0 0x00u /*!<@brief Pull Enable: Disables */
#define PCR_PFE_pfe0 0x00u /*!<@brief Passive Filter Enable: Disables */
#define PCR_PS_ps1 0x01u /*!<@brief Pull Select: Enables internal pullup resistor */
#define PCR_SRE_sre0 0x00u /*!<@brief Slew Rate Enable: Fast */
/*! @name PORT3_13 (number 37), P3_13/J1[14]
@{ */
/* Symbols to be used with GPIO driver */
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 13U /*!<@brief GPIO pin number */
#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 13U) /*!<@brief GPIO pin mask */
/* Symbols to be used with PORT driver */
#define BOARD_INITLEDSPINS_LED_GREEN_PORT PORT3 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITLEDSPINS_LED_GREEN_PIN 13U /*!<@brief PORT pin number */
#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PORT3_12 (number 38), P3_12/J1[12]/J5[1]
@{ */
/* Symbols to be used with GPIO driver */
#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 12U /*!<@brief GPIO pin number */
#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 12U) /*!<@brief GPIO pin mask */
/* Symbols to be used with PORT driver */
#define BOARD_INITLEDSPINS_LED_RED_PORT PORT3 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITLEDSPINS_LED_RED_PIN 12U /*!<@brief PORT pin number */
#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 12U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PORT3_0 (number 46), P3_0/J1[8]
@{ */
/* Symbols to be used with GPIO driver */
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 0U /*!<@brief GPIO pin number */
#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */
/* Symbols to be used with PORT driver */
#define BOARD_INITLEDSPINS_LED_BLUE_PORT PORT3 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITLEDSPINS_LED_BLUE_PIN 0U /*!<@brief PORT pin number */
#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitLEDsPins(void);
/*! @name PORT1_7 (number 1), P1_7/J1[1]
@{ */
/* Symbols to be used with GPIO driver */
#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 7U /*!<@brief GPIO pin number */
#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */
/* Symbols to be used with PORT driver */
#define BOARD_INITBUTTONSPINS_SW3_PORT PORT1 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITBUTTONSPINS_SW3_PIN 7U /*!<@brief PORT pin number */
#define BOARD_INITBUTTONSPINS_SW3_PIN_MASK (1U << 7U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PORT1_29 (number 8), P1_29/J3[6]/J18[10]
@{ */
/* Symbols to be used with GPIO driver */
#define BOARD_INITBUTTONSPINS_SW1_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITBUTTONSPINS_SW1_GPIO_PIN 29U /*!<@brief GPIO pin number */
#define BOARD_INITBUTTONSPINS_SW1_GPIO_PIN_MASK (1U << 29U) /*!<@brief GPIO pin mask */
/* Symbols to be used with PORT driver */
#define BOARD_INITBUTTONSPINS_SW1_PORT PORT1 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITBUTTONSPINS_SW1_PIN 29U /*!<@brief PORT pin number */
#define BOARD_INITBUTTONSPINS_SW1_PIN_MASK (1U << 29U) /*!<@brief PORT pin mask */
/* @} */
/*! @name PORT3_29 (number 32), P3_29/J18[7]/J4[11]
@{ */
/* Symbols to be used with GPIO driver */
#define BOARD_INITBUTTONSPINS_ISP_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */
#define BOARD_INITBUTTONSPINS_ISP_GPIO_PIN 29U /*!<@brief GPIO pin number */
#define BOARD_INITBUTTONSPINS_ISP_GPIO_PIN_MASK (1U << 29U) /*!<@brief GPIO pin mask */
/* Symbols to be used with PORT driver */
#define BOARD_INITBUTTONSPINS_ISP_PORT PORT3 /*!<@brief PORT peripheral base pointer */
#define BOARD_INITBUTTONSPINS_ISP_PIN 29U /*!<@brief PORT pin number */
#define BOARD_INITBUTTONSPINS_ISP_PIN_MASK (1U << 29U) /*!<@brief PORT pin mask */
/* @} */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitBUTTONsPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake
Vendored
+25
View File
@@ -0,0 +1,25 @@
set(MCU_VARIANT MCXA156)
set(MCU_FAMILY MCXA)
set(MCU_CORE MCXA156)
set(JLINK_DEVICE MCXA156_M33)
set(PYOCD_TARGET MCXA156)
set(NXPLINK_DEVICE MCXA156:MCXA156)
set(PORT 0)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_MCXA156VLH
BOARD_TUD_RHPORT=0
BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
CFG_EXAMPLE_VIDEO_READONLY
)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
)
target_include_directories(${TARGET} PUBLIC
${SDK_DIR}/${MCU_FAMILY}/periph1
)
endfunction()
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa156/board.h
Vendored
+69
View File
@@ -0,0 +1,69 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: Freedom MCXA156
url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA156
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_GPIO GPIO3
#define LED_CLK kCLOCK_GateGPIO3
#define LED_PIN 12 // red
#define LED_STATE_ON 0
// ISP button
#define BUTTON_GPIO GPIO0
#define BUTTON_CLK kCLOCK_GateGPIO0
#define BUTTON_PIN 6 //SW3
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART0
static inline void board_uart_init_clock(void) {
/* attach 12 MHz clock to LPUART0 (debug console) */
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
}
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa156/board.mk
Vendored
+18
View File
@@ -0,0 +1,18 @@
MCU_VARIANT = MCXA156
MCU_FAMILY = MCXA
MCU_CORE = MCXA156
PORT = 0
CPU_CORE = cortex-m33-nodsp-nofp
CFLAGS += \
-DCPU_MCXA156VLH \
-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
INC += \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph1
JLINK_DEVICE = MCXA156
PYOCD_TARGET = MCXA156
# flash using pyocd
flash: flash-jlink
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c
Vendored
+482
View File
@@ -0,0 +1,482 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v13.0
processor: MCXA156
package_id: MCXA156VLL
mcu_data: ksdk2_0
processor_version: 0.15.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_clock.h"
#include "clock_config.h"
#include "fsl_spc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
//extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockFRO96M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CPU_clock.outFreq, value: 12 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 12 MHz}
- {id: Slow_clock.outFreq, value: 3 MHz}
- {id: System_clock.outFreq, value: 12 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO24M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 24 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 6 MHz}
- {id: System_clock.outFreq, value: 24 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO24M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO24M configuration
******************************************************************************/
void BOARD_BootClockFRO24M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO48M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 12 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO48M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO48M configuration
******************************************************************************/
void BOARD_BootClockFRO48M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO64M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 64 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
- {id: FRO_HF_clock.outFreq, value: 64 MHz}
- {id: MAIN_clock.outFreq, value: 64 MHz}
- {id: Slow_clock.outFreq, value: 16 MHz}
- {id: System_clock.outFreq, value: 64 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
sources:
- {id: SCG.FIRC.outFreq, value: 64 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO64M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO64M configuration
******************************************************************************/
void BOARD_BootClockFRO64M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO96M
called_from_default_init: true
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 96 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
- {id: FRO_HF_clock.outFreq, value: 96 MHz}
- {id: MAIN_clock.outFreq, value: 96 MHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 96 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: CLKOUTDIV_HALT, value: Enable}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
sources:
- {id: SCG.FIRC.outFreq, value: 96 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO96M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO96M configuration
******************************************************************************/
void BOARD_BootClockFRO96M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
}
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h
Vendored
+169
View File
@@ -0,0 +1,169 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO24M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO24M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO24M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO48M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO48M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO48M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO64M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO64M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO64M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO96M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO96M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO96M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c
Vendored
+144
View File
@@ -0,0 +1,144 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v15.0
processor: MCXA156
package_id: MCXA156VLL
mcu_data: ksdk2_0
processor_version: 0.15.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
- {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
/* GPIO3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GateGPIO3);
/* PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT3);
/* GPIO3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
/* GPIO3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GateGPIO0);
/* PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* GPIO3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
/* PORT0: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* LPUART0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
/* PORT0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_RXD */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_2 (pin 78) is configured as LPUART0_RXD */
PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config);
const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_TXD */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_3 (pin 79) is configured as LPUART0_TXD */
PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h
Vendored
+51
View File
@@ -0,0 +1,51 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
Vendored
+25
View File
@@ -0,0 +1,25 @@
set(MCU_VARIANT MCXN947)
set(MCU_FAMILY MCXN)
set(MCU_CORE MCXN947_cm33_core0)
set(JLINK_DEVICE MCXN947_M33_0)
set(PYOCD_TARGET MCXN947)
set(NXPLINK_DEVICE MCXN947:MCXN947)
set(PORT 1)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_MCXN947VDF_cm33_core0
BOARD_TUD_RHPORT=${PORT}
# port 0 is fullspeed, port 1 is highspeed
BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
)
target_include_directories(${TARGET} PUBLIC
${SDK_DIR}/${MCU_FAMILY}/periph
)
endfunction()
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxn947/board.h
Vendored
+76
View File
@@ -0,0 +1,76 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: Freedom MCXN947
url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXN947
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_GPIO GPIO0
#define LED_CLK kCLOCK_Gpio0
#define LED_PIN 10 // red
#define LED_STATE_ON 0
// WAKE button (Dummy, use unused pin
#define BUTTON_GPIO GPIO0
#define BUTTON_CLK kCLOCK_Gpio0
#define BUTTON_PIN 23
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART4
#define LP_FLEXCOMM_INST 4
#include "fsl_lpflexcomm.h"
static inline void board_uart_init_clock(void) {
/* attach FRO 12M to FLEXCOMM4 */
LP_FLEXCOMM_Init(LP_FLEXCOMM_INST, LP_FLEXCOMM_PERIPH_LPUART);
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
}
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
Vendored
+18
View File
@@ -0,0 +1,18 @@
MCU_VARIANT = MCXN947
MCU_FAMILY = MCXN
MCU_CORE = MCXN947_cm33_core0
PORT ?= 1
CPU_CORE = cortex-m33
CFLAGS += \
-DCPU_MCXN947VDF_cm33_core0 \
-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
INC += \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph
JLINK_DEVICE = MCXN947_M33_0
PYOCD_TARGET = MCXN947
# flash using pyocd
flash: flash-jlink
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.c
Vendored
+338
View File
@@ -0,0 +1,338 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v10.0
processor: MCXN947
package_id: MCXN947VDF
mcu_data: ksdk2_0
processor_version: 0.12.3
board: MCX-N9XX-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "clock_config.h"
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
// extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockPLL150M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 12 MHz}
- {id: Slow_clock.outFreq, value: 3 MHz}
- {id: System_clock.outFreq, value: 12 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
}
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF48M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF48M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 12 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFROHF48M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFROHF48M configuration
******************************************************************************/
void BOARD_BootClockFROHF48M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
}
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF144M ********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF144M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 144 MHz}
- {id: MAIN_clock.outFreq, value: 144 MHz}
- {id: Slow_clock.outFreq, value: 18 MHz}
- {id: System_clock.outFreq, value: 72 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
sources:
- {id: SCG.FIRC.outFreq, value: 144 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFROHF144M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFROHF144M configuration
******************************************************************************/
void BOARD_BootClockFROHF144M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U); /*!< Set AHBCLKDIV divider to value 2 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL150M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL150M
called_from_default_init: true
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 150 MHz}
- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
- {id: Slow_clock.outFreq, value: 37.5 MHz}
- {id: System_clock.outFreq, value: 150 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: RunPowerMode, value: OD}
- {id: SCGMode, value: PLL0}
- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockPLL150M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockPLL150M configuration
******************************************************************************/
void BOARD_BootClockPLL150M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
/*!< Set up PLL0 */
const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL100M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CLK_IN_clock.outFreq, value: 24 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 100 MHz}
- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
- {id: Slow_clock.outFreq, value: 25 MHz}
- {id: System_clock.outFreq, value: 100 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: PLL1_Mode, value: Normal}
- {id: SCGMode, value: PLL1}
- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
sources:
- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockPLL100M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockPLL100M configuration
******************************************************************************/
void BOARD_BootClockPLL100M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupExtClocking(24000000U);
CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
/*!< Set up PLL1 */
const pll_setup_t pll1Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
.pllndiv = SCG_SPLLNDIV_NDIV(6U),
.pllpdiv = SCG_SPLLPDIV_PDIV(2U),
.pllmdiv = SCG_SPLLMDIV_MDIV(100U),
.pllRate = 100000000U
};
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
}
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxn947/clock_config.h
Vendored
+177
View File
@@ -0,0 +1,177 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF48M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFROHF48M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFROHF48M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFROHF48M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF144M ********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFROHF144M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */
#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFROHF144M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFROHF144M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL150M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockPLL150M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL150M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockPLL150M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockPLL100M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL100M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockPLL100M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.c
Vendored
+143
View File
@@ -0,0 +1,143 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v12.0
processor: MCXN947
package_id: MCXN947VDF
mcu_data: ksdk2_0
processor_version: 0.12.3
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
invert_input: normal}
- {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
- {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
/* Enables the clock for PORT0: Enables clock */
CLOCK_EnableClock(kCLOCK_Port0);
/* Enables the clock for PORT1: Enables clock */
CLOCK_EnableClock(kCLOCK_Port1);
const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as FC4_P0 */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT1_8 (pin A1) is configured as FC4_P0 */
PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as FC4_P1 */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT1_9 (pin B1) is configured as FC4_P1 */
PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PIO0_23 */
kPORT_MuxAlt0,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_23 (pin B7) is configured as PIO0_23 */
PORT_SetPinConfig(PORT0, 23U, &SW2);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/boards/frdm_mcxn947/pin_mux.h
Vendored
+51
View File
@@ -0,0 +1,51 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/boards/mcxn947brk/board.cmake
Vendored
+25
View File
@@ -0,0 +1,25 @@
set(MCU_VARIANT MCXN947)
set(MCU_FAMILY MCXN)
set(MCU_CORE MCXN947_cm33_core0)
set(JLINK_DEVICE MCXN947_M33_0)
set(PYOCD_TARGET MCXN947)
set(NXPLINK_DEVICE MCXN947:MCXN947)
set(PORT 1)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_MCXN947VDF_cm33_core0
BOARD_TUD_RHPORT=${PORT}
# port 0 is fullspeed, port 1 is highspeed
BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
)
target_include_directories(${TARGET} PUBLIC
${SDK_DIR}/${MCU_FAMILY}/periph
)
endfunction()
third_party/tinyusb/hw/bsp/mcx/boards/mcxn947brk/board.h
Vendored
+71
View File
@@ -0,0 +1,71 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: MCXN947 Breakout
url: n/a
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_GPIO GPIO3
#define LED_CLK kCLOCK_Gpio3
#define LED_PIN 4 // red
#define LED_STATE_ON 0
// WAKE button (Dummy, use unused pin
#define BUTTON_GPIO GPIO0
#define BUTTON_CLK kCLOCK_Gpio0
#define BUTTON_PIN 6
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART4
static inline void board_uart_init_clock(void) {
/* attach FRO 12M to FLEXCOMM4 */
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
}
//#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN
//#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif
third_party/tinyusb/hw/bsp/mcx/boards/mcxn947brk/board.mk
Vendored
+18
View File
@@ -0,0 +1,18 @@
MCU_VARIANT = MCXN947
MCU_FAMILY = MCXN
MCU_CORE = MCXN947_cm33_core0
PORT ?= 1
CPU_CORE = cortex-m33
CFLAGS += \
-DCPU_MCXN947VDF_cm33_core0 \
-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
INC += \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/periph
JLINK_DEVICE = MCXN947_M33_0
PYOCD_TARGET = MCXN947
# flash using pyocd
flash: flash-jlink
third_party/tinyusb/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
Vendored
+338
View File
@@ -0,0 +1,338 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v10.0
processor: MCXN947
package_id: MCXN947VDF
mcu_data: ksdk2_0
processor_version: 0.12.3
board: MCX-N9XX-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "clock_config.h"
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
// extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockPLL150M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 12 MHz}
- {id: Slow_clock.outFreq, value: 3 MHz}
- {id: System_clock.outFreq, value: 12 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
}
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF48M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF48M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 12 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFROHF48M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFROHF48M configuration
******************************************************************************/
void BOARD_BootClockFROHF48M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
}
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF144M ********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF144M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 144 MHz}
- {id: MAIN_clock.outFreq, value: 144 MHz}
- {id: Slow_clock.outFreq, value: 18 MHz}
- {id: System_clock.outFreq, value: 72 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
sources:
- {id: SCG.FIRC.outFreq, value: 144 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFROHF144M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFROHF144M configuration
******************************************************************************/
void BOARD_BootClockFROHF144M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U); /*!< Set AHBCLKDIV divider to value 2 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL150M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL150M
called_from_default_init: true
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 150 MHz}
- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
- {id: Slow_clock.outFreq, value: 37.5 MHz}
- {id: System_clock.outFreq, value: 150 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: RunPowerMode, value: OD}
- {id: SCGMode, value: PLL0}
- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockPLL150M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockPLL150M configuration
******************************************************************************/
void BOARD_BootClockPLL150M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
/*!< Set up PLL0 */
const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL100M
outputs:
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CLK_IN_clock.outFreq, value: 24 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 100 MHz}
- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
- {id: Slow_clock.outFreq, value: 25 MHz}
- {id: System_clock.outFreq, value: 100 MHz}
- {id: gdet_clock.outFreq, value: 48 MHz}
- {id: trng_clock.outFreq, value: 48 MHz}
settings:
- {id: PLL1_Mode, value: Normal}
- {id: SCGMode, value: PLL1}
- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
sources:
- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockPLL100M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockPLL100M configuration
******************************************************************************/
void BOARD_BootClockPLL100M(void)
{
/*!< Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
CLOCK_SetupExtClocking(24000000U);
CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
/*!< Set up PLL1 */
const pll_setup_t pll1Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
.pllndiv = SCG_SPLLNDIV_NDIV(6U),
.pllpdiv = SCG_SPLLPDIV_PDIV(2U),
.pllmdiv = SCG_SPLLMDIV_MDIV(100U),
.pllRate = 100000000U
};
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
}
third_party/tinyusb/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
Vendored
+177
View File
@@ -0,0 +1,177 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF48M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFROHF48M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFROHF48M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFROHF48M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF144M ********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFROHF144M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */
#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockFROHF144M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFROHF144M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL150M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockPLL150M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL150M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockPLL150M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockPLL100M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL100M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockPLL100M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */
third_party/tinyusb/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
Vendored
+141
View File
@@ -0,0 +1,141 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v12.0
processor: MCXN947
package_id: MCXN947VDF
mcu_data: ksdk2_0
processor_version: 0.12.3
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
invert_input: normal}
- {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
- {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
/* Enables the clock for PORT1: Enables clock */
CLOCK_EnableClock(kCLOCK_Port1);
/* Enables the clock for PORT3: Enables clock */
CLOCK_EnableClock(kCLOCK_Port3);
const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as FC4_P0 */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT1_8 (pin A1) is configured as FC4_P0 */
PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as FC4_P1 */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT1_9 (pin B1) is configured as FC4_P1 */
PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as PIO3_4 */
kPORT_MuxAlt0,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT3_4 (pin F14) is configured as PIO3_4 */
PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
Vendored
+51
View File
@@ -0,0 +1,51 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
third_party/tinyusb/hw/bsp/mcx/debug.jlinkscript
Vendored
+5
View File
@@ -0,0 +1,5 @@
int SetupTarget(void) {
JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
return 0;
}
third_party/tinyusb/hw/bsp/mcx/drivers/spc/fsl_spc.c
Vendored
+1680
View File
File diff suppressed because it is too large. Load diff
third_party/tinyusb/hw/bsp/mcx/drivers/spc/fsl_spc.h
Vendored
+2433
View File
File diff suppressed because it is too large. Load diff
third_party/tinyusb/hw/bsp/mcx/family.c
Vendored
+235
View File
@@ -0,0 +1,235 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
manufacturer: NXP
*/
#include "bsp/board_api.h"
#include "fsl_device_registers.h"
#include "fsl_gpio.h"
#include "fsl_lpuart.h"
#include "board.h"
#include "pin_mux.h"
#include "clock_config.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
#if CFG_TUSB_MCU == OPT_MCU_MCXN9
void USB0_FS_IRQHandler(void) {
tusb_int_handler(0, true);
}
void USB1_HS_IRQHandler(void) {
tusb_int_handler(1, true);
}
#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
void USB0_IRQHandler(void) {
tusb_int_handler(0, true);
}
#endif
void board_init(void) {
BOARD_InitBootPins();
BOARD_InitBootClocks();
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// Explicitly disable systick to prevent its ISR from running before scheduler start
SysTick->CTRL &= ~1U;
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
#if CFG_TUSB_MCU == OPT_MCU_MCXN9
NVIC_SetPriority(USB0_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#else
NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
#endif
// LED
CLOCK_EnableClock(LED_CLK);
gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0};
GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
board_led_write(0);
#ifdef NEOPIXEL_PIN
// No neo pixel support yet
#endif
// Button
#ifdef BUTTON_GPIO
CLOCK_EnableClock(BUTTON_CLK);
gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
#endif
#ifdef UART_DEV
// Enable UART when debug log is on
board_uart_init_clock();
lpuart_config_t uart_config;
LPUART_GetDefaultConfig(&uart_config);
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
uart_config.enableTx = true;
uart_config.enableRx = true;
LPUART_Init(UART_DEV, &uart_config, 12000000u);
#endif
// USB VBUS
/* PORT0 PIN22 configured as USB0_VBUS */
#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
// Port0 is Full Speed
#if CFG_TUSB_MCU == OPT_MCU_MCXA15
RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
#elif CFG_TUSB_MCU == OPT_MCU_MCXN9
CLOCK_AttachClk(kCLK_48M_to_USB0);
CLOCK_EnableClock(kCLOCK_Usb0Ram);
CLOCK_EnableClock(kCLOCK_Usb0Fs);
#endif
CLOCK_EnableUsbfsClock();
#endif
#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
// Port1 is High Speed
// Power
SPC0->ACTIVE_VDELAY = 0x0500;
/* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
/* Wait until it is done */
while (SPC0->SC & SPC_SC_BUSY_MASK) {}
if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
SCG0->TRIM_LOCK = 0x5a5a0001U;
SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
/* wait LDO ready */
while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
}
SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
/* xtal = 20 ~ 30MHz */
SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
while (1) {
if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
break;
}
}
// Clock
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
CLOCK_EnableClock(kCLOCK_UsbHs);
CLOCK_EnableClock(kCLOCK_UsbHsPhy);
CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
CLOCK_EnableUsbhsClock();
// USB PHY
#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
#endif
// Enable PHY support for Low speed device + LS via FS Hub
USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
// Enable all power for normal operation
USBPHY->PWD = 0;
// TX Timing
uint32_t phytx = USBPHY->TX;
phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
//phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
USBPHY->TX = phytx;
#endif
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state) {
GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
}
uint32_t board_button_read(void) {
#ifdef BUTTON_GPIO
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
#endif
}
int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
return -1;
}
int board_uart_write(void const* buf, int len) {
#ifdef UART_DEV
const uint8_t *p = (const uint8_t *) buf;
int count = 0;
while (count < len) {
if (UART_DEV->STAT & LPUART_STAT_TDRE_MASK) {
UART_DEV->DATA = p[count];
count++;
} else {
break;
}
}
return count;
#else
(void) buf; (void) len;
return -1;
#endif
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler(void) {
system_ticks++;
}
uint32_t tusb_time_millis_api(void) {
return system_ticks;
}
#endif
third_party/tinyusb/hw/bsp/mcx/family.cmake
Vendored
+140
View File
@@ -0,0 +1,140 @@
include_guard()
set(MCUX_DIR ${TOP}/hw/mcu/nxp/mcuxsdk-core)
set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-devices-mcx)
set(CMSIS_DIR ${TOP}/lib/CMSIS_6)
# include board specific
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
if (MCU_VARIANT STREQUAL "MCXA153")
set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
elseif (MCU_VARIANT STREQUAL "MCXA156")
set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
elseif (MCU_VARIANT STREQUAL "MCXN947")
set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
else()
message(FATAL_ERROR "MCU_VARIANT not supported")
endif()
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
#------------------------------------
# Startup & Linker script
#------------------------------------
if (NOT DEFINED LD_FILE_GNU)
set(LD_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
endif ()
set(LD_FILE_Clang ${LD_FILE_GNU})
if (NOT DEFINED STARTUP_FILE_GNU)
set(STARTUP_FILE_GNU ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
endif()
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
if (NOT DEFINED LD_FILE_IAR)
set(LD_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/${MCU_CORE}_flash.icf)
endif ()
if (NOT DEFINED STARTUP_FILE_IAR)
set(STARTUP_FILE_IAR ${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/iar/startup_${MCU_CORE}.s)
endif ()
#------------------------------------
# Board Target
#------------------------------------
function(family_add_board BOARD_TARGET)
add_library(${BOARD_TARGET} STATIC
# driver
${MCUX_DIR}/drivers/gpio/fsl_gpio.c
${MCUX_DIR}/drivers/common/fsl_common_arm.c
${MCUX_DIR}/drivers/lpuart/fsl_lpuart.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c
# mcu
${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/system_${MCU_CORE}.c
${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_clock.c
${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers/fsl_reset.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${CMSIS_DIR}/CMSIS/Core/Include
${MCUX_DIR}/drivers/gpio/
${MCUX_DIR}/drivers/lpuart
${MCUX_DIR}/drivers/common
${MCUX_DIR}/drivers/port
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc
${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}
${SDK_DIR}/${MCU_FAMILY}/${MCU_VARIANT}/drivers
)
if (${FAMILY_MCUS} STREQUAL "MCXN9")
target_sources(${BOARD_TARGET} PRIVATE
${MCUX_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${MCUX_DIR}/drivers/lpflexcomm
)
elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
endif()
update_board(${BOARD_TARGET})
endfunction()
#------------------------------------
# Functions
#------------------------------------
function(family_configure_example TARGET RTOS)
family_configure_common(${TARGET} ${RTOS})
if (${FAMILY_MCUS} STREQUAL "MCXN9")
family_add_tinyusb(${TARGET} OPT_MCU_MCXN9)
elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
family_add_tinyusb(${TARGET} OPT_MCU_MCXA15)
endif()
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
)
target_include_directories(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
)
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${TARGET} PUBLIC
"LINKER:--script=${LD_FILE_GNU}"
--specs=nosys.specs --specs=nano.specs
"LINKER:--defsym=__stack_size__=0x1000"
"LINKER:--defsym=__heap_size__=0"
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
target_link_options(${TARGET} PUBLIC
"LINKER:--script=${LD_FILE_Clang}"
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${TARGET} PUBLIC
"LINKER:--config=${LD_FILE_IAR}"
"LINKER:--config_def=__stack_size__=0x1000"
"LINKER:--config_def=__heap_size__=0"
)
endif ()
if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
set_source_files_properties(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c PROPERTIES COMPILE_FLAGS "-Wno-missing-prototypes")
endif ()
set_source_files_properties(${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} PROPERTIES
SKIP_LINTING ON
COMPILE_OPTIONS -w)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
#family_flash_pyocd(${TARGET})
endfunction()
third_party/tinyusb/hw/bsp/mcx/family.mk
Vendored
+69
View File
@@ -0,0 +1,69 @@
UF2_FAMILY_ID = 0x2abc77ec
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m33
MCUX_DIR = hw/mcu/nxp/mcuxsdk-core
SDK_DIR = hw/mcu/nxp/mcux-devices-mcx
# Default to Highspeed PORT1
PORT ?= 1
CFLAGS += \
-flto \
-DBOARD_TUD_RHPORT=$(PORT) \
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls
LDFLAGS += \
--specs=nosys.specs --specs=nano.specs \
-Wl,--defsym=__stack_size__=0x1000 \
-Wl,--defsym=__heap_size__=0 \
# All source paths should be relative to the top level.
LD_FILE ?= $(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
ifeq ($(PORT), 1)
$(info "PORT1 High Speed")
CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
else
$(info "PORT0 Full Speed")
CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
endif
SRC_C += \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/system_$(MCU_CORE).c \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_clock.c \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers/fsl_reset.c \
$(TOP)/$(MCUX_DIR)/drivers/gpio/fsl_gpio.c \
$(TOP)/$(MCUX_DIR)/drivers/lpuart/fsl_lpuart.c \
$(TOP)/$(MCUX_DIR)/drivers/common/fsl_common_arm.c \
hw/bsp/mcx/drivers/spc/fsl_spc.c
# fsl_lpflexcomm for MCXN9
ifeq ($(MCU_VARIANT), MCXN947)
SRC_C += $(MCUX_DIR)/drivers/lpflexcomm/fsl_lpflexcomm.c
endif
# fsl_spc for MCXNA15
ifeq ($(MCU_VARIANT), MCXA153)
endif
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/CMSIS_6/CMSIS/Core/Include \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT) \
$(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/drivers \
$(TOP)/$(MCUX_DIR)/drivers/ \
$(TOP)/$(MCUX_DIR)/drivers/lpuart \
$(TOP)/$(MCUX_DIR)/drivers/lpflexcomm \
$(TOP)/$(MCUX_DIR)/drivers/common \
$(TOP)/$(MCUX_DIR)/drivers/gpio \
$(TOP)/$(MCUX_DIR)/drivers/port \
$(TOP)/hw/bsp/mcx/drivers/spc
SRC_S += $(TOP)/$(SDK_DIR)/$(MCU_FAMILY)/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S