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@@ -0,0 +1,22 @@
set(MCU_VARIANT rx65n)
set(MCU_FAMILY RX65X)
set(CMAKE_SYSTEM_CPU rx64m CACHE INTERNAL "System Processor")
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/r5f565ne.ld)
set(JLINK_DEVICE R5F565NE)
set(JLINK_IF JTAG)
set(RFP_DEVICE rx65x)
set(RFP_TOOL e2l)
set(BOARD_SOURCES
${CMAKE_CURRENT_LIST_DIR}/rx65n_target.c
)
function(update_board TARGET)
target_include_directories(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
)
endfunction()
@@ -0,0 +1,71 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: RX65N Target Board
url: https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n
*/
#ifndef BOARD_H_
#define BOARD_H_
#include "iodefine.h"
#ifdef __cplusplus
extern "C" {
#endif
// LED: PD6, active low (open-drain)
#define BOARD_LED_WRITE(state) (PORTD.PODR.BIT.B6 = (state) ? 0 : 1)
// Button: PB1, active low
#define BOARD_BUTTON_READ() (PORTB.PIDR.BIT.B1 ? 0 : 1)
// UART: SCI5
#define BOARD_UART_SCI SCI5
#define BOARD_SCI_TXI_HANDLER INT_Excep_SCI5_TXI5
#define BOARD_SCI_TEI_HANDLER INT_Excep_ICU_GROUPBL0 // SCI5 TEI uses group interrupt
#define BOARD_SCI_RXI_HANDLER INT_Excep_SCI5_RXI5
// USB interrupt handler (software configurable vector)
#define IRQ_USB0_USBI0 62
#define SLIBR_USBI0 SLIBR185
#define IR_USB0_USBI0 IR_PERIB_INTB185
#define IER_USB0_USBI0 IER_PERIB_INTB185
#define IEN_USB0_USBI0 IEN_PERIB_INTB185
#define IPR_USB0_USBI0 IPR_PERIB_INTB185
#define INT_Excep_USB0_USBI0 INT_Excep_PERIB_INTB185
#define BOARD_USB_IRQ_HANDLER INT_Excep_USB0_USBI0
// Clocks
#define BOARD_PCLK 60000000
#define BOARD_CPUCLK 120000000
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H_ */
@@ -0,0 +1,25 @@
CFLAGS += \
-mcpu=rx64m \
-misa=v2 \
-DCFG_TUSB_MCU=OPT_MCU_RX65X \
-DIR_USB0_USBI0=IR_PERIB_INTB185 \
-DIER_USB0_USBI0=IER_PERIB_INTB185 \
-DIEN_USB0_USBI0=IEN_PERIB_INTB185
MCU_DIR = hw/mcu/renesas/rx/rx65n
# All source paths should be relative to the top level.
LD_FILE = $(BOARD_PATH)/r5f565ne.ld
# For freeRTOS port source
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RX600
# For flash-jlink target
JLINK_DEVICE = R5F565NE
JLINK_IF = JTAG
# For flash-pyocd target
PYOCD_TARGET =
# flash using rfp-cli
flash: flash-rfp
@@ -0,0 +1,168 @@
__USTACK_SIZE = 0x00000800;
__ISTACK_SIZE = 0x00000800;
MEMORY
{
RAM : ORIGIN = 0x4, LENGTH = 0x3fffc
RAM2 : ORIGIN = 0x00800000, LENGTH = 0x60000
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128
ROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000
}
SECTIONS
{
.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
{
"_exvectors_start" = .;
KEEP(*(.exvectors))
"_exvectors_end" = .;
} >ROM
.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
{
KEEP(*(.fvectors))
} > ROM
.text 0xFFE00000: AT(0xFFE00000)
{
*(.text)
*(.text.*)
*(P)
KEEP(*(.text.*_isr))
etext = .;
} > ROM
.rvectors ALIGN(4):
{
_rvectors_start = .;
KEEP(*(.rvectors))
_rvectors_end = .;
} > ROM
.init :
{
KEEP(*(.init))
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
__init_array_start = (. + 3) & ~ 3;
KEEP(*(.init_array))
KEEP(*(SORT(.init_array.*)))
__init_array_end = .;
__fini_array_start = .;
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
__fini_array_end = .;
} > ROM
.fini :
{
KEEP(*(.fini))
} > ROM
.got :
{
*(.got)
*(.got.plt)
} > ROM
.rodata :
{
*(.rodata)
*(.rodata.*)
*(C_1)
*(C_2)
*(C)
_erodata = .;
} > ROM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > ROM
.eh_frame :
{
*(.eh_frame)
} > ROM
.jcr :
{
*(.jcr)
} > ROM
.tors :
{
__CTOR_LIST__ = .;
. = ALIGN(2);
___ctors = .;
*(.ctors)
___ctors_end = .;
__CTOR_END__ = .;
__DTOR_LIST__ = .;
___dtors = .;
*(.dtors)
___dtors_end = .;
__DTOR_END__ = .;
. = ALIGN(2);
_mdata = .;
} > ROM
.data : AT(_mdata)
{
_data = .;
*(.data)
*(.data.*)
*(D)
*(D_1)
*(D_2)
_edata = .;
} > RAM
.gcc_exc :
{
*(.gcc_exc)
} > RAM
.bss :
{
_bss = .;
*(.bss)
*(.bss.**)
*(COMMON)
*(B)
*(B_1)
*(B_2)
_ebss = .;
_end = .;
} > RAM
.ustack :
{
. = ALIGN(8);
. = . + __USTACK_SIZE;
PROVIDE(_ustack = .);
} > RAM
.istack :
{
. = ALIGN(8);
. = . + __ISTACK_SIZE;
PROVIDE(_istack = .);
} > RAM
.ofs1 0xFE7F5D00: AT(0xFE7F5D00)
{
KEEP(*(.ofs1))
} > OFS
.ofs2 0xFE7F5D10: AT(0xFE7F5D10)
{
KEEP(*(.ofs2))
} > OFS
.ofs3 0xFE7F5D20: AT(0xFE7F5D20)
{
KEEP(*(.ofs3))
} > OFS
.ofs4 0xFE7F5D40: AT(0xFE7F5D40)
{
KEEP(*(.ofs4))
} > OFS
.ofs5 0xFE7F5D48: AT(0xFE7F5D48)
{
KEEP(*(.ofs5))
} > OFS
.ofs6 0xFE7F5D50: AT(0xFE7F5D50)
{
KEEP(*(.ofs6))
} > OFS
.ofs7 0xFE7F5D64: AT(0xFE7F5D64)
{
KEEP(*(.ofs7))
} > OFS
.ofs8 0xFE7F5D70: AT(0xFE7F5D70)
{
KEEP(*(.ofs8))
} > OFS
}
@@ -0,0 +1,147 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Koji Kitayama
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* How to connect JLink and RX65n Target and option board
* (For original comment https://github.com/hathach/tinyusb/pull/922#issuecomment-869786131)
*
* To enable JTAG, RX65N requires following connections on main board.
* - short EJ2 jumper header, to disable onboard E2L.
* - short EMLE(J1-2) and 3V3(J1-14 or J2-10), to enable In-Circuit Emulator.
*
* Note: For RX65N-Cloud-Kit, the option board's JTAG pins to some switches or floating.
* To use JLink with the option board, I think some further modifications will be necessary.
*
* | Function | RX65N pin | main board | option board | JLink connector |
* |:---------:|:----------:|:----------:|:------------:|:---------------:|
* | 3V3 | VCC | J1-14 | CN5-6 | 1 |
* | TRST | P34 | J1-16 | CN5-7 | 3 |
* | GND | VSS | J1-12 | CN5-5 | 4 |
* | TDI | P30 | J1-20 | CN5-10 | 5 |
* | TMS | P31 | J1-19 | USER_SW | 7 |
* | TCK/FINEC | P27 | J1-21 | N/A | 9 |
* | TDO | P26 | J1-22 | CN5-9 | 13 |
* | nRES | RES# | J1-10 | RESET_SW | 15 |
*
* JLink firmware needs to update to V6.96 or newer version to avoid
* [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
* regarding downloading.
*/
#include "iodefine.h"
#include "board.h"
#define SYSTEM_PRCR_PRC1 (1<<1)
#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
#define MPC_PFS_ISEL (1<<6)
#define IRQ_PRIORITY_SCI5 5
#define SCI_PCLK 60000000
void HardwareSetup(void)
{
FLASH.ROMCIV.WORD = 1;
while (FLASH.ROMCIV.WORD) ;
FLASH.ROMCE.WORD = 1;
while (!FLASH.ROMCE.WORD) ;
SYSTEM.PRCR.WORD = 0xA503u;
if (!SYSTEM.RSTSR1.BYTE) {
RTC.RCR4.BYTE = 0;
RTC.RCR3.BYTE = 12;
while (12 != RTC.RCR3.BYTE) ;
}
SYSTEM.SOSCCR.BYTE = 1;
if (SYSTEM.HOCOCR.BYTE) {
SYSTEM.HOCOCR.BYTE = 0;
while (!SYSTEM.OSCOVFSR.BIT.HCOVF) ;
}
SYSTEM.PLLCR.WORD = 0x1D10u; /* HOCO x 15 */
SYSTEM.PLLCR2.BYTE = 0;
while (!SYSTEM.OSCOVFSR.BIT.PLOVF) ;
SYSTEM.SCKCR.LONG = 0x21C11222u;
SYSTEM.SCKCR2.WORD = 0x0041u;
SYSTEM.ROMWT.BYTE = 0x02u;
while (0x02u != SYSTEM.ROMWT.BYTE) ;
SYSTEM.SCKCR3.WORD = 0x400u;
SYSTEM.PRCR.WORD = 0xA500u;
}
void board_pin_init(void)
{
/* Setup software configurable interrupts for USB */
ICU.SLIBR_USBI0.BYTE = IRQ_USB0_USBI0;
ICU.SLIPRCR.BYTE = 1;
/* Unlock MPC registers */
MPC.PWPR.BIT.B0WI = 0;
MPC.PWPR.BIT.PFSWE = 1;
/* Button PB1 */
PORTB.PMR.BIT.B1 = 0U;
PORTB.PDR.BIT.B1 = 0U;
/* LED PD6 (open-drain, active low) */
PORTD.PODR.BIT.B6 = 1U;
PORTD.ODR1.BIT.B4 = 1U;
PORTD.PMR.BIT.B6 = 0U;
PORTD.PDR.BIT.B6 = 1U;
/* UART TXD5 => PA4, RXD5 => PA3 */
PORTA.PMR.BIT.B4 = 1U;
PORTA.PCR.BIT.B4 = 1U;
MPC.PA4PFS.BYTE = 0b01010;
PORTA.PMR.BIT.B3 = 1U;
MPC.PA3PFS.BYTE = 0b01010;
/* USB VBUS -> P16 */
PORT1.PMR.BIT.B6 = 1U;
MPC.P16PFS.BYTE = MPC_PFS_ISEL | 0b10001;
/* Lock MPC registers */
MPC.PWPR.BIT.PFSWE = 0;
MPC.PWPR.BIT.B0WI = 1;
/* Enable SCI5 */
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
MSTP(SCI5) = 0;
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
SCI5.SEMR.BIT.ABCS = 1;
SCI5.SEMR.BIT.BGDM = 1;
SCI5.BRR = (SCI_PCLK / (8 * 115200)) - 1;
IR(SCI5, RXI5) = 0;
IR(SCI5, TXI5) = 0;
IS(SCI5, TEI5) = 0;
IR(ICU, GROUPBL0) = 0;
IPR(SCI5, RXI5) = IRQ_PRIORITY_SCI5;
IPR(SCI5, TXI5) = IRQ_PRIORITY_SCI5;
IPR(ICU,GROUPBL0) = IRQ_PRIORITY_SCI5;
IEN(SCI5, RXI5) = 1;
IEN(SCI5, TXI5) = 1;
IEN(ICU,GROUPBL0) = 1;
EN(SCI5, TEI5) = 1;
}