382 lines
12 KiB
ArmAsm
382 lines
12 KiB
ArmAsm
/*
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* Copyright (c) 2019 Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* \file startup_gd32vf103.S
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* \brief NMSIS Nuclei N/NX Class Core based Core Device Startup File for
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* Device gd32vf103
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* \version V1.00
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* \date 21 Nov 2019
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*
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*
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******************************************************************************/
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#include "riscv_encoding.h"
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.macro DECLARE_INT_HANDLER INT_HDL_NAME
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#if defined(__riscv_xlen) && (__riscv_xlen == 32)
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.word \INT_HDL_NAME
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#else
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.dword \INT_HDL_NAME
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#endif
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.endm
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.section .text.vtable
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.weak eclic_msip_handler
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.weak eclic_mtip_handler
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.weak eclic_bwei_handler
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.weak eclic_pmovi_handler
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.weak WWDGT_IRQHandler
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.weak LVD_IRQHandler
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.weak TAMPER_IRQHandler
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.weak RTC_IRQHandler
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.weak FMC_IRQHandler
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.weak RCU_IRQHandler
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.weak EXTI0_IRQHandler
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.weak EXTI1_IRQHandler
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.weak EXTI2_IRQHandler
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.weak EXTI3_IRQHandler
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.weak EXTI4_IRQHandler
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.weak DMA0_Channel0_IRQHandler
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.weak DMA0_Channel1_IRQHandler
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.weak DMA0_Channel2_IRQHandler
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.weak DMA0_Channel3_IRQHandler
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.weak DMA0_Channel4_IRQHandler
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.weak DMA0_Channel5_IRQHandler
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.weak DMA0_Channel6_IRQHandler
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.weak ADC0_1_IRQHandler
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.weak CAN0_TX_IRQHandler
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.weak CAN0_RX0_IRQHandler
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.weak CAN0_RX1_IRQHandler
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.weak CAN0_EWMC_IRQHandler
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.weak EXTI5_9_IRQHandler
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.weak TIMER0_BRK_IRQHandler
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.weak TIMER0_UP_IRQHandler
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.weak TIMER0_TRG_CMT_IRQHandler
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.weak TIMER0_Channel_IRQHandler
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.weak TIMER1_IRQHandler
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.weak TIMER2_IRQHandler
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.weak TIMER3_IRQHandler
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.weak I2C0_EV_IRQHandler
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.weak I2C0_ER_IRQHandler
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.weak I2C1_EV_IRQHandler
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.weak I2C1_ER_IRQHandler
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.weak SPI0_IRQHandler
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.weak SPI1_IRQHandler
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.weak USART0_IRQHandler
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.weak USART1_IRQHandler
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.weak USART2_IRQHandler
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.weak EXTI10_15_IRQHandler
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.weak RTC_Alarm_IRQHandler
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.weak USBFS_WKUP_IRQHandler
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.weak EXMC_IRQHandler
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.weak TIMER4_IRQHandler
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.weak SPI2_IRQHandler
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.weak UART3_IRQHandler
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.weak UART4_IRQHandler
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.weak TIMER5_IRQHandler
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.weak TIMER6_IRQHandler
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.weak DMA1_Channel0_IRQHandler
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.weak DMA1_Channel1_IRQHandler
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.weak DMA1_Channel2_IRQHandler
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.weak DMA1_Channel3_IRQHandler
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.weak DMA1_Channel4_IRQHandler
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.weak CAN1_TX_IRQHandler
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.weak CAN1_RX0_IRQHandler
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.weak CAN1_RX1_IRQHandler
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.weak CAN1_EWMC_IRQHandler
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.weak USBFS_IRQHandler
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.globl vector_base
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.type vector_base, @object
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vector_base:
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j _start /* 0: Reserved, Jump to _start when reset for vector table not remapped cases.*/
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.align LOG_REGBYTES /* Need to align 4 byte for RV32, 8 Byte for RV64 */
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DECLARE_INT_HANDLER default_intexc_handler /* 1: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 2: Reserved */
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DECLARE_INT_HANDLER eclic_msip_handler /* 3: Machine software interrupt */
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DECLARE_INT_HANDLER default_intexc_handler /* 4: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 5: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 6: Reserved */
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DECLARE_INT_HANDLER eclic_mtip_handler /* 7: Machine timer interrupt */
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DECLARE_INT_HANDLER default_intexc_handler /* 8: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 9: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 10: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 11: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 12: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 13: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 14: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 15: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */
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DECLARE_INT_HANDLER eclic_bwei_handler /* 17: Bus Error interrupt */
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DECLARE_INT_HANDLER eclic_pmovi_handler /* 18: Performance Monitor */
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DECLARE_INT_HANDLER WWDGT_IRQHandler
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DECLARE_INT_HANDLER LVD_IRQHandler
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DECLARE_INT_HANDLER TAMPER_IRQHandler
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DECLARE_INT_HANDLER RTC_IRQHandler
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DECLARE_INT_HANDLER FMC_IRQHandler
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DECLARE_INT_HANDLER RCU_IRQHandler
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DECLARE_INT_HANDLER EXTI0_IRQHandler
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DECLARE_INT_HANDLER EXTI1_IRQHandler
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DECLARE_INT_HANDLER EXTI2_IRQHandler
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DECLARE_INT_HANDLER EXTI3_IRQHandler
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DECLARE_INT_HANDLER EXTI4_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel0_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel1_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel2_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel3_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel4_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel5_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel6_IRQHandler
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DECLARE_INT_HANDLER ADC0_1_IRQHandler
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DECLARE_INT_HANDLER CAN0_TX_IRQHandler
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DECLARE_INT_HANDLER CAN0_RX0_IRQHandler
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DECLARE_INT_HANDLER CAN0_RX1_IRQHandler
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DECLARE_INT_HANDLER CAN0_EWMC_IRQHandler
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DECLARE_INT_HANDLER EXTI5_9_IRQHandler
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DECLARE_INT_HANDLER TIMER0_BRK_IRQHandler
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DECLARE_INT_HANDLER TIMER0_UP_IRQHandler
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DECLARE_INT_HANDLER TIMER0_TRG_CMT_IRQHandler
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DECLARE_INT_HANDLER TIMER0_Channel_IRQHandler
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DECLARE_INT_HANDLER TIMER1_IRQHandler
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DECLARE_INT_HANDLER TIMER2_IRQHandler
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DECLARE_INT_HANDLER TIMER3_IRQHandler
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DECLARE_INT_HANDLER I2C0_EV_IRQHandler
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DECLARE_INT_HANDLER I2C0_ER_IRQHandler
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DECLARE_INT_HANDLER I2C1_EV_IRQHandler
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DECLARE_INT_HANDLER I2C1_ER_IRQHandler
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DECLARE_INT_HANDLER SPI0_IRQHandler
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DECLARE_INT_HANDLER SPI1_IRQHandler
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DECLARE_INT_HANDLER USART0_IRQHandler
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DECLARE_INT_HANDLER USART1_IRQHandler
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DECLARE_INT_HANDLER USART2_IRQHandler
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DECLARE_INT_HANDLER EXTI10_15_IRQHandler
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DECLARE_INT_HANDLER RTC_Alarm_IRQHandler
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DECLARE_INT_HANDLER USBFS_WKUP_IRQHandler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER EXMC_IRQHandler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER TIMER4_IRQHandler
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DECLARE_INT_HANDLER SPI2_IRQHandler
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DECLARE_INT_HANDLER UART3_IRQHandler
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DECLARE_INT_HANDLER UART4_IRQHandler
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DECLARE_INT_HANDLER TIMER5_IRQHandler
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DECLARE_INT_HANDLER TIMER6_IRQHandler
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DECLARE_INT_HANDLER DMA1_Channel0_IRQHandler
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DECLARE_INT_HANDLER DMA1_Channel1_IRQHandler
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DECLARE_INT_HANDLER DMA1_Channel2_IRQHandler
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DECLARE_INT_HANDLER DMA1_Channel3_IRQHandler
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DECLARE_INT_HANDLER DMA1_Channel4_IRQHandler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER default_intexc_handler
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DECLARE_INT_HANDLER CAN1_TX_IRQHandler
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DECLARE_INT_HANDLER CAN1_RX0_IRQHandler
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DECLARE_INT_HANDLER CAN1_RX1_IRQHandler
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DECLARE_INT_HANDLER CAN1_EWMC_IRQHandler
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DECLARE_INT_HANDLER USBFS_IRQHandler
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.section .text.init
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.globl _start
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.type _start, @function
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/**
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* Reset Handler called on controller reset
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*/
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_start:
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/* ===== Startup Stage 1 ===== */
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/* Disable Global Interrupt */
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csrc CSR_MSTATUS, MSTATUS_MIE
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/* Jump to logical address first to ensure correct operation of RAM region */
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la a0, _start
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li a1, 1
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slli a1, a1, 29
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bleu a1, a0, _start0800
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srli a1, a1, 2
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bleu a1, a0, _start0800
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la a0, _start0800
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add a0, a0, a1
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jr a0
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_start0800:
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/* Initialize GP and Stack Pointer SP */
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.option push
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.option norelax
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la gp, __global_pointer$
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la tp, __tls_base
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.option pop
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la sp, _sp
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/*
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* Set the the NMI base mnvec to share
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* with mtvec by setting CSR_MMISC_CTL
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* bit 9 NMI_CAUSE_FFF to 1
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*/
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li t0, MMISC_CTL_NMI_CAUSE_FFF
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csrs CSR_MMISC_CTL, t0
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/*
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* Intialize ECLIC vector interrupt
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* base address mtvt to vector_base
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*/
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la t0, vector_base
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csrw CSR_MTVT, t0
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/*
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* Set ECLIC non-vector entry to be controlled
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* by mtvt2 CSR register.
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* Intialize ECLIC non-vector interrupt
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* base address mtvt2 to irq_entry.
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*/
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la t0, irq_entry
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csrw CSR_MTVT2, t0
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csrs CSR_MTVT2, 0x1
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/*
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* Set Exception Entry MTVEC to early_exc_entry
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* Due to settings above, Exception and NMI
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* will share common entry.
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* This early_exc_entry is only used during early
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* boot stage before main
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*/
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la t0, early_exc_entry
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csrw CSR_MTVEC, t0
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/* Set the interrupt processing mode to ECLIC mode */
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li t0, 0x3f
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csrc CSR_MTVEC, t0
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csrs CSR_MTVEC, 0x3
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/* ===== Startup Stage 2 ===== */
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#if defined(__riscv_flen) && __riscv_flen > 0
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/* Enable FPU, and set state to initial */
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li t0, MSTATUS_FS
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csrc mstatus, t0
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li t0, MSTATUS_FS_INITIAL
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csrs mstatus, t0
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#endif
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/* Enable mcycle and minstret counter */
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csrci CSR_MCOUNTINHIBIT, 0x5
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/* ===== Startup Stage 3 ===== */
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/*
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* Load text section from CODE ROM to CODE RAM
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* when text LMA is different with VMA
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*/
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la a0, _text_lma
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la a1, _text
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/* If text LMA and VMA are equal
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* then no need to copy text section */
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beq a0, a1, 2f
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la a2, _etext
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bgeu a1, a2, 2f
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1:
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/* Load code section if necessary */
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* Load data section */
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la a0, _data_lma
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la a1, _data
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* Clear bss section */
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la a0, __bss_start
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la a1, _end
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/*
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* Call vendor defined SystemInit to
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* initialize the micro-controller system
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*/
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call SystemInit
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/* Call global constructors */
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la a0, __libc_fini_array
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call atexit
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/* Call C/C++ constructor start up code */
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call __libc_init_array
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/* do pre-init steps before main */
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call _premain_init
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/*
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* When all initialization steps done
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* set exception entry to correct exception
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* entry and jump to main.
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* And set the interrupt processing mode to
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* ECLIC mode
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*/
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la t0, exc_entry
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csrw CSR_MTVEC, t0
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li t0, 0x3f
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csrc CSR_MTVEC, t0
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csrs CSR_MTVEC, 0x3
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/* ===== Call Main Function ===== */
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/* argc = argv = 0 */
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li a0, 0
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li a1, 0
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#ifdef RTOS_RTTHREAD
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// Call entry function when using RT-Thread
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call entry
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#else
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call main
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#endif
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/* do post-main steps after main */
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call _postmain_fini
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1:
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j 1b
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/* Early boot exception entry before main */
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.align 6
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.global early_exc_entry
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early_exc_entry:
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wfi
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j early_exc_entry
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